There's still some silly clause-level packing required, but this way the
register slots are at least assigned correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Although it's software-defined, this stems from architectural traits and
is useful in both the disasm and the compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Table instructions are a subset of those scheduled to the ADD unit. They
typically involve lookup tables. Table (TBL) instructions have
additional restrictions on their sources which the scheduler must
respect.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
If this instruction must be the last in the clause.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Stubs due to some edge cases, for the scheduler.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Someone who understands meson and gtest could do something much nicer,
but for now let's just stuff some assertions into debug builds of the
standalone compiler and call it a day...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Takes offset *but not swizzle* into account, so the scheduler can
predict whether indices will end up mapped to the same scalar register.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Needs to take a cursor to be applicable outside NIR->BIR of course.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Abstracts over *CUBEFACE1/+CUBEFACE2, takes the sources of the former
and outputs two destinations.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
If an index is an SSA form and we haven't even written to it yet, there
is absolutely no value in filling it, it'd just be uninitialized garbage
that won't get used. Saves some fills in STK.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
We use essentially the same logic, but we need to treat entire clauses
as large instructions, and spill on clause boundaries instead of
instruction boundaries. So factor out the code a bit, using the new
iterators, removing bi_unwrap_singleton.
A few specific fixes are needed to adapt. One is simple: rewriting
destinations needs to preserve clamps and such. The other is a much more
subtle bug. Consider the clause
{
ADD 0, ...
---unrelated code---
MUL 1, 0, ...
}
Suppose we spill 0. The naive spill code would generate an SSA temporary to
spill to and another SSA temporary to fill from, generating:
{
LOAD.tl 10
}
{
ADD 11, ...
---unrelated code---
MUL 1, 10, ...
}
{
STORE.tl 11
}
But this is wrong; the MUL now reads stale (and for SSA, likely
undefined/uninitialized) data. The simplest fix, employed here, is to
spill/fill within a clause simultaneously, which means the temporary
can't be SSA, generating correct code:
{
LOAD.tl r0
}
{
ADD r0, ...
---unrelated code---
MUL 1, r0, ...
}
{
STORE.tl r0
}
This is suboptimal, since the LOAD is still likely reading garbage that
is unused. But it is still correct, and the next commit will avoid
generating the load in this case.
To make the bug even more subtle, if ADD/MUL are within 2-3 instructions
of each other, the scheduler will optimize the load to a
temporary/passthrough, so the bug isn't noticed. It only happens if they
are 3+ instructions apart yet still in the same clause (<=16
instructions).
Special thanks to macc24 for reporting this bug and to Jason Ekstrand
for allowing me to rubberduck.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
These are convenient for post-sched passes, in particular register
allocation. They work by noting the underlying linked list of
instructions in the block must be preserved by scheduling. It isn't
necessary iterate the clause structure directly, it can simply be used
to bound a iteration within the block by recalling clauses are strictly
contained in a single block.
<alyssa> I don't think I'm enough of a C ninja to write fancy iterator macros yet.
<zmike> sometimes those can get pretty mind-bendy
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Written in a funny way but easy to convince yourself of correctness by
considering cases.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Will be needed to insert spill code after scheduling once we have
multiple instructions in a clause.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
We would like to reuse the DCE logic to eliminate register writes
without eliminating instructions, as a post-sched pass. This type of
operation will eventually generalize to intrinsics that write a register
*and* have side effects (just atomics, I think).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Ported from Midgard due to the same quirk of our code generation.
Additional validation, though.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
I want to transition away from the ad hoc masks anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
C's definition of the % operator has a footgun around sign conversion.
Avoid it and just use bitwise arithemtic instead like the hardware
would, fixing the disassembly and making buggy assembly more obvious.
Fixes: 08a9e5e3e8 ("pan/bi: Decode M values in disasm")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Unconditional branches have a successor in the first slot only.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Writes are from the previous tuple, not the current one, otherwise we
incorrectly write to "two" places at once and raise an INSTR_INVALID_ENC
fault. While we're at it, fix the weird spacing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Was incorrectly returning zero. Special case like IDLE_1.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
I would make this unconditional, but conditionally branching to the same
clause in a tight loop is (disturbingly) legal, as far as I know.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Let's get the offset in a named variable for validation.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Even if we're not loading a uniform, this is useful information. The
uniform pretty-printing didn't correspond well to the hardware anyway so
this is a net win, although if somebody really wanted pretty-printing
could be added in here.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
We were throwing away this information. Let's just use a lookup table
and add an assertion. Would have caught a bug in this series resulting
in INSTR_INVALID_ENC faults.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Since 3186401751 ("pan/bi: Suppress disassembly for internal shaders"),
we haven't had a good way to debug blit shaders. I keep rewriting this
patch manually, let's just a debug flag for it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
I don't understand the underlying uarch details but ATEST needs to wait
on slot 6 and BLEND needs to wait on both, so these bits are used if
ATEST/BLEND are in the first clause, which happens if e.g. a constant
colour is written, or if the input is preloaded.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Alyssa Rosenzweig