Commit Graph

16 Commits

Author SHA1 Message Date
Eric Anholt bf29daa1b5 ci/deqp: Switch to a new dEQP runner written in Rust.
I found the C++ runner hard to develop on, and we had stability issues and
outstanding feature needs that made me want something I felt good about
hacking on.  Thus, Rewrite It In Rust of the deqp runner.

The new runner includes:

- Skip lists don't reshuffle the test list.
- Known-flake handling without resorting to skip lists (fixing our main CI
  reliability issue on a3xx right now).
- Per-thread Vulkan shader caches should speed up VK CI runtime.
- Tracking of crashes separate from fails (so we can see progress on that
  front).
- Logging of deqp stderr spam (particularly assertion failures!) in the CI
  log.
- Integrated QPA filtering so we don't have bash perf issues for it.
- Logging of what caselist to go look at for a given error report (in red,
  so it's easier to find in your CI log).
- The code is 1/3 unit tests, and easy to extend for more coverage.
- Non-LAVA CI runs create a failures.csv in artifacts that you can check
  in as your deqp-*-fails.txt file.
- Test runtime is included in results.csv so you can debug how to speed up
  your CI job.
- Pretty summary at the end of the run of slow/flaky/failed tests.

Since this is a new runner with a different RNG, the test groups are
shuffled one more time.  This seems to result in some panfrost T720
stability issues (See its new deqp-panfrost-t720-flakes.txt), and one new
flake in freedreno a630.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7434>
2020-11-06 19:48:39 +00:00
Icenowy Zheng 9205762cae lima: implement zsbuf reload
Fragment shader can write depth and stencil if we set necessary flags
in RSW. In addition to that we need to use special format for Z24S8.
Original format is apparently Z24X8 since we can't sample stencil in GLES2.
This new format also seems to use several components for storing depth
since we saw r != g != b when sampling with this format.

[vasily: - initialize clear->depth to 0xffffff if we reload depth, just
           like blob does. Reloading doesn't work otherwise
         - use single bitmap for reload type]

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Vasily Khoruzhick 2756b62917 lima/gpir: add better lowering for ftrunc
GP doesn't support ftrunc natively and unfortunately one in generic
opt_algebraic is not GP-friendly either. Introduce our own lowering
that utilizes fsign() that GP supports:
ftrunc(a) = fmul(fsign(a), ffloor(fmax(a, -a)))

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
2020-03-16 16:28:33 -07:00
Vasily Khoruzhick b7d89476f1 lima/gpir: kill dead writes to regs in DCE
Writes to regs that are never read will confuse regalloc since they
are never live and don't conflict with any regs. Kill them to prevent
overwriting another live reg.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
2020-03-16 23:08:06 +00:00
Andreas Baierl e58bb417b5 lima: Add etc1 support
Layer stride has to be divided by 4. We also have to take care of
the array_size when returning the bo_size.

Drop the affected tests from the fails list.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3946>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3946>
2020-03-02 10:33:06 +00:00
Andreas Baierl 31a8075678 gitlab-ci: lima: Add flaky tests to the skips list
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
2020-02-25 07:45:53 +00:00
Qiang Yu ed117ee630 lima: move clear into submit (v2)
clear info is needed when submit flush and may be changed after
framebuffer switch, so we need to move it into submit.

This also fixes 5 dEQP tests as a side effect: clear info is per
submit so clear value when one submit won't affect next submit.

v2:
remove fixed dEQP test from CI list.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Eric Anholt 658eb691fc ci: Bump the GLES CTS version to 3.2.6.1.
This brings in the surfaceless fixes so we don't need to check out the
whole repo to cherry pick any more (which was bothering me as I debugged
things late in the painfully slow ARM container build process).

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3662>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3662>
2020-02-06 15:18:24 -08:00
Erico Nunes 4ca3de06ec lima/ppir: fix ssa undef emit
The ssa doesn't need to be manually added to block->comp->reg_list.
Doing so actually causes other registers to be marked as undef=true
later.

This patch alone fixes a few deqp tests that have undefs.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
2020-01-25 14:48:55 +01:00
Erico Nunes d6b1917c01 lima/ppir: handle write to dead registers in ppir
nir can output writes to dead registers when expanding vec4 operations
to non-ssa registers. In that case, some components of the vec4 may be
assigned but never read. These are also not currently removed by a nir
dead code elimination pass as they are not ssa.
In order to prevent regalloc from allocating a live register for this
operation, an interference must be assigned to it during liveness
analysis.

This workaround may be removed in the future if the assignments to dead
components can be removed earlier in ppir or nir.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
2020-01-25 14:48:02 +01:00
Vasily Khoruzhick e470116aac ci: Re-enable CI for lima on mali450
Amend fails and skips lists basing on lists from Andreas Baierl,
shard mali400 job across two devices since it takes close to 10min
and rename jobs to lima-mali400-test and lima-mali450-test.

Also don't set MESA_GLES_VERSION_OVERRIDE=3.0 for lima since we don't support
GLES 3.0 and lower DEQP_PARALLEL to 3 for jobs on H3.

Keep mali400 jobs disabled atm since they take too much time to complete
and we also get some unexplicable failures in dEQP-GLES2.functional.default_vertex_attrib.*

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>
2020-01-21 09:33:57 +00:00
Vasily Khoruzhick 65a5b24aee lima: add support for gl_PointSize
GP handles gl_PointSize similar to gl_Position, i.e. it needs
separate buffer and it has special type in varying descriptors, also
for indexed draw we need to emit special PLBU command to pass
address of gl_PointSize buffer.

Blob also clamps gl_PointSize to 1 .. 100 (as well as line width),
so let's do the same.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-05 17:44:56 -08:00
Vasily Khoruzhick 103378f332 lima: set dithering flag when necessary
Bit 13 in aux1 enables dithering

Reviewed-by: Qiang.Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-01 21:44:31 -07:00
Arno Messiaen a9391a1a01 lima: add cubemap support
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2019-10-31 06:29:31 +00:00
Chris Wilson 0899bf55d4 st/mesa: Map MESA_FORMAT_RGB_UNORM8 <-> PIPE_FORMAT_R8G8B8_UNORM
This is useful for PBO texture upload with GL_RGB and GL_UNSIGNED_BYTE.

v2: Vasily Khoruzhick provided an update for the Lima CI expectations.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-10-22 22:13:14 +00:00
Tomeu Vizoso 6397dff6d7 gitlab-ci/lava: Test Lima driver with dEQP
Run dEQP on boards with Mali 400 and 450 in Baylibre's lab.

There's lots of skipped tests because of crashes and undetermined
behavior. May be a good idea to run the tests with valgrind and fix any
issues found.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-10 14:50:14 +00:00