Less IFETCH latency on misses. Shader code is write once read many,
so GTT doesn't make much sense anyway.
If it turns out to fragment the CPU visible VRAM too much, we can upload with SDMA.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This adds gs copy shader support to the pipeline cache, and few
geometry related changes.
v2: rebase for spill changes.
v2.1: fix incorrect pipeline destruction.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Also changed RADV_SHOW_QUEUES to a no compute queue option. That
would make more sense later when the compute queue is established,
but the transfer queue still experimental.
v2: Don't include the trace flag.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
No sense in repeatedly determining it. Also, it might be dependent
on the device as shaders get compiled differently for SI/CIK/VI etc.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
This moves to the shared vk_alloc inlines for vulkan
memory allocations.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This squashes all the radv development up until now into
one for merging.
History can be found:
https://github.com/airlied/mesa/tree/semi-interesting
This requires llvm 3.9 and is in no way considered
a conformant vulkan implementation. It can run a number
of vulkan applications, and supports all GPUs using
the amdgpu kernel driver.
Thanks to Intel for providing anv and spirv->nir,
and Emil Velikov for reviewing build integration.
Parts of this are:
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Authors: Bas Nieuwenhuizen and Dave Airlie
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri
Bas Nieuwenhuizen
Dave Airlie
Grigori Goronzy