Commit Graph

81629 Commits

Author SHA1 Message Date
Rob Clark e8beffb1b3 nir/validate: dump annotated shader with error msgs
Log all the errors, and at the end dump the shader w/ error annotations
to make it easier to see where the problems are.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2016-05-17 10:05:20 -04:00
Rob Clark 54ecfcc162 nir/validate: assert() -> validate_assert()
Prep work for next patch.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2016-05-17 10:05:20 -04:00
Rob Clark a0ef26c1c2 nir/print: add support for print annotations
Caller can pass a hashtable mapping NIR object (currently instr or var,
but I guess others could be added as needed) to annotation msg to print
inline with the shader dump.  As the annotation msg is printed, it is
removed from the hashtable to give the caller a way to know about any
unassociated msgs.

This is used in the next patch, for nir_validate to try to associate
error msgs to nir_print dump.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2016-05-17 10:05:20 -04:00
Alejandro Piñeiro e5e412cd27 i965: Expose OpenGL 4.2 for gen8+
ARB_vertex_attrib_64bit was the only feature missing.

v2: we can expose 4.2 instead of 4.1 (Ian Romanick)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:55 +02:00
Alejandro Piñeiro f051eae25a docs: Mark ARB_vertex_attrib_64bit as done for i965/gen8+
v2: label as done for i965/gen8+ instead of i965 (Kenneth Graunke)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:55 +02:00
Alejandro Piñeiro 59b5441fd9 i965: Enable ARB_vertex_attrib_64bit for gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:55 +02:00
Juan A. Suarez Romero d6281a9d95 i965: take care of doubles when lowering VS inputs
Input attributes can require 2 vec4 or 1 vec4 depending on whether they
are double-precision or not.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:55 +02:00
Juan A. Suarez Romero 7ea09511ca i965/fs: calculate first non-payload GRF using attrib slots
When computing where the first non-payload GRF starts, we can't rely on
the number of attributes, as each attribute can be using 1 or 2 slots
depending on whether they are a dvec3/4 or other.

Instead, we need to use the number of slots used by the attributes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:55 +02:00
Juan A. Suarez Romero b7423b485e i965/vec4: use attribute slots to calculate URB read length
Do not use total attributes because a dvec3/dvec4 attribute requires two
slots. So rather use total attribute slots.

v2: do not use loop to calculate required attribute slots (Kenneth
Graunke)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:55 +02:00
Juan A. Suarez Romero b0fb08e179 i965: take care of doubles when remapping VS attributes
Double-precision types require 1 slot in VUE for double and dvec2, and 2 slots for
anything else.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:54 +02:00
Juan A. Suarez Romero 80535873bb nir: add double input bitmap
This bitmap tracks which input attributes are double-precision.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:54 +02:00
Juan A. Suarez Romero ccfe25f758 i965/fs: shuffle 32bits into 64bits for doubles
VS Thread Payload handles attributes in URB as vec4, no matter if they
are actually single or double precision.

So with double-precision types, value ends up in the registers split in
32bits chunks, in different positions.

We need to shuffle the chunks to get the doubles correctly.

v2:
 * Extra blank line. Add { } on if body (Ian Romanick)
 * Use dest directly (Kenneth Graunke)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 09:05:47 +02:00
Alejandro Piñeiro 96c276dda9 i965/fs: half exec_size when dealing with 64 bits attributes
The HW has a restriction that only vertical stride may cross register
boundaries. Until now this was only handled on VGRFs at
rw_reg_from_fs_reg, but it is also needed for attributes.

v2:
 * Remove reference to commit id on commit message (Juan Suarez)
 * Simplify code that compute final exec_size (Ian Romanick)
 * Use REG_SIZE on that same code (Kenneth Graunke)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 07:34:40 +02:00
Alejandro Piñeiro 1ff32ae8b2 i965: passthru formats cannot be used width edge flag enabled
Add an assertion to detect this case.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 07:34:40 +02:00
Antia Puentes 8b0a334b5e i965: Configure how to store *64*PASSTHRU vertex components
From the Broadwell specification, structure VERTEX_ELEMENT_STATE
description:

   "When SourceElementFormat is set to one of the *64*_PASSTHRU
    formats,  64-bit components are stored in the URB without any
    conversion. In this case, vertex elements must be written as 128
    or 256 bits, with VFCOMP_STORE_0 being used to pad the output
    as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red component into
    the URB, Component 1 must be specified as VFCOMP_STORE_0 (with
    Components 2,3 set to VFCOMP_NOSTORE) in order to output a 128-bit
    vertex element, or Components 1-3 must be specified as VFCOMP_STORE_0
    in order to output a 256-bit vertex element. Likewise, use of
    R64G64B64_PASSTHRU requires Component 3 to be specified as VFCOMP_STORE_0
    in order to output a 256-bit vertex element."

Uses 128-bits to write double and dvec2 vertex elements, and 256-bits for
dvec3 and dvec4 vertex elements.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Antia Puentes <apuentes@igalia.com>

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 07:34:40 +02:00
Alejandro Piñeiro 71150b73c8 i965: get the proper vertex surface type for doubles on gen8+
This commit adds support for PASSTHRU format when pushing
double-precision attributes.

Check glarray->Doubles in order to know if we should choose a format
that does a conversion to float, or just passthru the 64-bit double.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-17 07:34:40 +02:00
Ilia Mirkin b1d74e9486 nvc0/ir: make sure out-of-bounds buffer loads/atomics get a 0 result
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-05-17 01:27:29 -04:00
Timothy Arceri 4fb4fd0b6b glsl: make reserved_varying_slot() static
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-05-17 15:06:39 +10:00
Timothy Arceri 1d752823af glsl: include per-patch varyings when generating reserved slot bitfield
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-05-17 15:06:27 +10:00
Timothy Arceri 00441829e7 glsl: don't incorrectly eliminate patches with explicit locations
These varying have a separate location domain from per-vertex varyings
and need to be handled separately.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-05-17 15:06:21 +10:00
Timothy Arceri 3f477f0ea5 glsl: remove remainings tabs in link_varyings.cpp
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-05-17 15:06:16 +10:00
Timothy Arceri 6d5f7557fb glsl: fix location and component packing validation on patches
These varyings have a separate location domain from per-vertex varyings
and need to be handled separately.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-05-17 15:06:12 +10:00
Kenneth Graunke aae0865dc0 i965: Enable ARB_shader_precision on Gen8+.
I recently fixed a bug in the Piglit tests:
https://lists.freedesktop.org/archives/piglit/2016-May/019802.html

With that patch in place, we pass all the tests.  So, turn it on.

We could probably expose this earlier than Gen8, but the extension
says that OpenGL 4.0 is required, and all of our tests are written
against GLSL 4.00 (which is only supported on Gen8+).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 17:52:45 -07:00
Jose Fonseca cf010de6ee vl/dri: Move the DRI3 check out of sources include into C.
Fixes SCons build.

Trivial.  Built locally with SCons and autotools.
2016-05-16 21:50:43 +01:00
Leo Liu 5e2072c711 st/vdpau: add dri3 support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu c122c74dca vl/dri3: implement functions for get and set timestamp
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 9f50a79b8f vl/dri3: handle PresentCompleteNotify event
and get timestamp calculated based on the event's reply

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu e8282178ab st/va: add dri3 support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 8d7ac0a4e4 vl/dri3: implement DRI3 BufferFromPixmap
We also need render to the front buffer of temporary X pixmap,
this is the case of when we using opengl as video out for vaapi.
the basic implementation is to pass pixmap ID to X server, and
then X will return dma-buf fd, we will get the buffer object
through this dma-buf fd.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 858b329c2c vl/dri3: add support for resizing
When drawable size changed, PresentConfigureNotify event will be
emitted, by handling the event to re-allocate resized buffer.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 96580ad593 vl/dri3: implement funciton for get dirty area
This will clear presentation area not covered by video content

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu b0bd908284 vl/dri3: implement function for flush frontbuffer
Request drawable content in pixmap by calling DRI3 PresentPixmap,
and handle PresentIdleNotify event.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu e1223282db vl/dri3: add back buffers support
This implements DRI3 PixmapFromBuffer. Create buffer objects, and
associate it to a dma-buf fd, and then pass this fd with a pixmap
ID to X server for creating pixmap object; also add a function
for wait events.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 69ba9be4d2 vl/dri3: implement flushing for queued events
also place holder for present events handling

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 758b1bbaa7 vl/dri3: register present events
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 672e8d5e7e vl/dri3: set drawable geometry
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu 12e5220e34 vl/dri3: add DRI3 support and implement create and destroy
Required functions into place for implementation, create screen
with device fd returned from X server, also bail out to DRI2
with certain conditions.

v2: -organize the error out path (Axel)
    -squash previous patch 1 and 2 into one (Emil)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Dave Airlie 30e437bd76 mesa/version.c: enable cull distance in version check.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-17 06:08:31 +10:00
Ian Romanick 11096ecc39 glsl/linker: Include the interface name for input and output blocks
On my oes_shader_io_blocks branch, this fixes 71
dEQP-GLES31.functional.program_interface_query.* tests.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2016-05-16 11:18:03 -07:00
Ian Romanick 7c11589eb4 glsl/linker: Use canonical format for ARB_program_interface_query spec quotes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 11:18:03 -07:00
Mark Janes fd854c1add i965: check tcs for NULL dereference
Coverity issue 1361544 found an instance where the tcs variable is
checked for NULL, but unconditionally dereferenced later in the same
function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 11:11:11 -07:00
Matt Turner bf91034d44 i965: Mark is_lossless_compressed_aux UNUSED to silence warning.
Used only in assert().
2016-05-16 11:08:55 -07:00
Matt Turner 1385018a72 genxml: Use llroundf() and store to appropriate type.
Both functions return uint64_t, so I expect the masking/shifting should
be done on 64-bit types.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2016-05-16 11:06:15 -07:00
Matt Turner 4191551262 nir: Mark nir_start_block()/nir_impl_last_block() with returns_nonnull.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 11:06:15 -07:00
Matt Turner 377ab2f2d7 util: Add ATTRIBUTE_RETURNS_NONNULL.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 11:06:15 -07:00
Jan Vesely 40c6d54e76 clover: grid_offset should be padded with 0 not 1
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-05-16 13:58:14 -04:00
Iago Toral Quiroga 71465179fc i965: Expose OpenGL 4.0 for gen8+
ARB_gpu_shader_fp64 was the only feature missing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 09:55:34 +02:00
Iago Toral Quiroga b1d21e1159 docs: Mark ARB_gpu_shader_fp64 as done for i965/gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 09:55:33 +02:00
Iago Toral Quiroga 309d285c6b i965: Enable ARB_gpu_shader_fp64 for gen8+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-16 09:55:33 +02:00
Iago Toral Quiroga 58f304defe i965/tes/scalar: Fix load input for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-05-16 09:55:33 +02:00