Commit Graph

138277 Commits

Author SHA1 Message Date
Connor Abbott c68ea960a7 ir3, tu: Add compiler flag for robust UBO behavior
This needs to be part of the compiler because it's the only piece that
we always have access to in all the places ir3_optimize_loop() is
called, and it's only enabled for the whole Vulkan device. Right now
it's just used for constraining vectorization, but the next commit adds
another use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
2021-04-15 16:05:11 +02:00
Connor Abbott 8f54028479 ir3: Reduce max const file indirect offset base to 9 bits
This fixes
dEQP-VK.robustness.robustness2.bind.notemplate.r32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.len_260.samples_1.1d.frag,
which accesses the shader UBO with c<a0.x + 512> due to the constant
data UBO coming before it in the const file. The len_256 variant has a
smaller constant data UBO, so it uses c<a0.x + 256> instead, and that
works, so 512 seems to be the real limit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
2021-04-15 16:03:54 +02:00
Connor Abbott 8e11f0560e ir3: Fix list corruption in legalize_block()
We forgot to remove the instruction under consideration from instr_list
before inserting it into the block's list, which caused instr_list to
become corrupted. This happened to work but caused further corruption in
some rare scenarios.

Fixes: adf1659 ("freedreno/ir3: use standard list implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
2021-04-15 16:03:54 +02:00
Gustavo Padovan f601fd635b gitlab-ci: enable Intel AML-Y as experimental
The LAVA lab has been running well with the rammus chromebook for some
time now. Let's add it to MesaCI as experimental to get more testing,
and later enable it in production.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10238>
2021-04-15 13:03:19 +00:00
Gustavo Padovan e8bc0a28a4 traces-iris: fix expectation for Intel GLK
glmark2/buffer-columns=200:interleave=true:update-dispersion=0.9:upd...
was missing the expectation checksum.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10238>
2021-04-15 13:03:19 +00:00
Iago Toral Quiroga bed3f31fc6 v3dv: don't use a dedicated BO for each occlusion query
Dedicated BOs waste memory and are also a significant cause of CPU
overhead when applications use hundreds of them per frame due to
all the work the kernel has to do to page in all these BOs for a job.
The UE4 Vehicle demo was hitting this causing it to freeze and stutter
under 1fps.

The hardware allows us to setup groups of 16 queries in consecutive
4-byte addresses, requiring only that each group of 16 queries is
aligned to a 1024 byte boundary. With this change, we allocate all
the queries in a pool in a single BO and we assign them different
offsets based on the above restriction. This eliminates the freezes
and stutters in the Vehicle sample.

One caveat of this solution is that we can only wait or test for
completion of a query by testing if the GPU is still using its BO,
which basically means that we can only wait for all active queries
in a pool to complete and not just the ones being requested by the
API. Since the Vulkan recommendation is to use a different query
pool per frame this should not be a big issue though.

If this ever becomes a problem (for example if an application does't
follow the recommendation and instead allocates a single pool and
splits its queries between frames), we could try to group queries
in a pool into a number of BOs to try and find a balance, but for
now this should work fine in most cases.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10253>
2021-04-15 12:45:07 +00:00
Mike Blumenkrantz a43da5c999 docs: update GL_ARB_texture_filter_minmax for zink
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
2021-04-15 12:35:09 +00:00
Mike Blumenkrantz cca616ebd5 zink: export PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
2021-04-15 12:35:09 +00:00
Mike Blumenkrantz 92f5006814 zink: handle minmax sampler creation for VK_EXT_sampler_filter_minmax
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
2021-04-15 12:35:09 +00:00
Mike Blumenkrantz 22e1ed5722 zink: support format queries for VK_EXT_sampler_filter_minmax
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
2021-04-15 12:35:09 +00:00
Mike Blumenkrantz b62633c599 zink: hook up VK_EXT_sampler_filter_minmax
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
2021-04-15 12:35:09 +00:00
Rhys Perry ec70882238 radv: fix barrier in radv_decompress_dcc_compute shader
ACO doesn't create a waitcnt for barriers between texture samples and
image stores because texture samples are supposed to use read-only
memory. It could also schedule the barrier to above the texture sample.
We also have use a larger memory scope to avoid an ACO optimization.

Tested on GFX8 with Sachsa Willems deferred sample. With some DCC
decompressions and the compute path forced.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9496>
2021-04-15 12:02:36 +00:00
Hans-Kristian Arntzen 08fdaec473 radv: Allocate buffer list for MUTABLE descriptor types as well.
Fixes: 86644b84b9 ("radv: Implement VK_VALVE_mutable_descriptor_type.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10132>
2021-04-15 11:51:33 +00:00
Hans-Kristian Arntzen b60bc59180 radv: Take image alignment into account when allocating MUTABLE pool.
Allocating a descriptor set is aligned to 32 bytes, so just like the
other buffer types, bump the descriptor size to 32 bytes when allocating
MUTABLE descriptor types from a pool.

Fixes: 86644b84b9 ("radv: Implement VK_VALVE_mutable_descriptor_type.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10132>
2021-04-15 11:51:33 +00:00
Karol Herbst f945cca983 clover/llvm: handle Fixed vs Scalable vectors explicitly starting with llvm-11
This fixes compilation with llvm-13.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4200
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9973>
2021-04-15 11:39:47 +00:00
Iago Toral Quiroga 917049e7d6 v3dv: fix array sizes when tracking BOs during uniform setup
The resource indices we get point to descriptor map entries that include
all shader stages, so we need to size the arrays to account for more than
just one stage.

For now we only support up to 2 stages in a pipeline, so we use that.

Fixes: 002304482c ('v3dv: avoid redundant BO job additions for UBO/SSBO')
Fixes: fa170dab4c ('v3dv: avoid redundant BO job additions for textures and samplers')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10252>
2021-04-15 11:26:04 +00:00
Iago Toral Quiroga e7e8464d94 v3dv: fix descriptor set limits
There were various issues here:
   - MAX_DYNAMIC_UNIFORM_BUFFERS was larger than MAX_UNIFORM_BUFFERS.
   - In some cases we were exposing more than the minimums required.
     While that is not incorrect, it is not following what we have
     been doing in general.
   - The Vulkan spec states that some of the MaxDescriptorSet limits
     need to be multipled by 6 to include all shader stages, even
     if the implementation doesn't support all shader stages.

Fixes: cbd299b051 ('v3dv/device: do not compute per-pipeline limits multiplying per-stage')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10252>
2021-04-15 11:26:04 +00:00
Alejandro Piñeiro a0152c5948 v3dv/debug: use gl stage when checking debug flag
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10229>
2021-04-15 10:29:44 +00:00
Alejandro Piñeiro 98698c4d01 v3dv/debug: print correct stage name
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10229>
2021-04-15 10:29:44 +00:00
Eric Anholt 6d510fd473 ci/freedreno: Merge a630 piglit to a single job.
piglit_gl clocked in at 6:12 end-to-end runtime, and piglit_shader spent
2:53 in deqp-runner, so merging them together should be about 9 minutes.
Removing a boot should save us a minute or two of runner time per
pipeline.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10243>
2021-04-15 10:06:14 +00:00
Simon Ser 35e25ea1d0 ac/surface: allow non-DCC modifiers for YUV on GFX9+
Accept non-linear tiling for multi-planar formats on GFX9+, as long
as DCC is disabled. DCC support is possible in theory, but untested
for now.

GFX8 is still restricted to linear tiling because it's not yet clear
how modifiers should be handled on these chips for multi-planar
formats. Each plane may need a different modifier.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
2021-04-15 09:43:17 +00:00
Simon Ser 979e138695 radeonsi: stop special-casing YUV formats in si_query_dmabuf_modifiers
Instead of having a special case for YUV formats in
si_query_dmabuf_modifiers, let ac_get_supported_modifiers handle
them. Keep setting external_only = 1 for YUV formats, since we
can only sample from such formats (we can't use them as render
targets).

This shouldn't change si_query_dmabuf_modifiers's behavior, because
for YUV formats ac_get_supported_modifiers will return a single
LINEAR modifier.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
2021-04-15 09:43:17 +00:00
Simon Ser 19378dfe3c ac/surface: use blocksizebits instead of blocksize
util_format_get_blocksize asserts that the blocksize isn't zero.
However the blocksize will be zero if the format's channel encoding
is unspecified. The channel encoding is only meaningful for the
plain u_format layout, so util_format_get_blocksize can't be used
for formats with another layout. For example, YUV formats don't have
the channel encoding specified.

Use util_format_get_blocksizebits, which just returns zero without
an assertion for formats which don't have a channel encoding.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
2021-04-15 09:43:17 +00:00
Simon Ser 6e697b595f util/format: document block depth field
After the pixel block width and height, a third field is used to
store the pixel block depth. Document this field.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
2021-04-15 09:43:17 +00:00
Simon Ser b26a546b2f radeon/vcn: handle tiled buffers when decoding
Set the swizzle mode when decoding.

Add a safe-guard to make sure the provided surface isn't DCC, because
we don't handle this situation.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
2021-04-15 09:43:17 +00:00
Samuel Iglesias Gonsálvez 029bc53be6 turnip: fix typo in tu_CmdBeginRenderPass2()
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:51:25 +02:00
Samuel Iglesias Gonsálvez d52917f858 turnip/lrz: added support for depth bounds test enable
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:51:25 +02:00
Samuel Iglesias Gonsálvez 2161aebf8d turnip: document GRAS_LRZ_CNTL's UNK5 bitfield
It is used by the blob to enable depth bounds test for LRZ.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:51:25 +02:00
Samuel Iglesias Gonsálvez 54cf12774a turnip/lrz: add support for VK_EXT_extended_dynamic_state
When the depth or stencil state changes dynamically, that might affect
LRZ state and we need to recalculate it and emit it again.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:51:20 +02:00
Samuel Iglesias Gonsálvez 6d6cbb7361 turnip: refactor how LRZ state is calculated
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:50:51 +02:00
Samuel Iglesias Gonsálvez 43ebba4e88 turnip: initialize pipeline->rb_{stencil,depth}_cntl always
This change will simplify further changes on LRZ state management.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:50:51 +02:00
Samuel Iglesias Gonsálvez 1f9fb7677b turnip: move pipeline gras_su and rb{stencil,depth}_cntl_mask initialization
Move them up, so they are initialized even when the dynamic state is
not used.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
2021-04-15 09:50:51 +02:00
Iago Toral Quiroga b8403192ed v3dv: use a bitfield to implement a quick check for job BO tracking
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10210>
2021-04-15 06:09:34 +00:00
Iago Toral Quiroga 9e76240f84 v3dv: optimize a few cases of BO job additions
In these cases we know that the BO has not been added to the job
before, so we can skip the usual process for adding the BO where
we check if we had already added it before to avoid duplicates.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10210>
2021-04-15 06:09:34 +00:00
Iago Toral Quiroga 493a316e40 v3dv: avoid redundant BO job additions for spill / shared BOs
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10210>
2021-04-15 06:09:34 +00:00
Iago Toral Quiroga 002304482c v3dv: avoid redundant BO job additions for UBO/SSBO
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10210>
2021-04-15 06:09:34 +00:00
Iago Toral Quiroga fa170dab4c v3dv: avoid redundant BO job additions for textures and samplers
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10210>
2021-04-15 06:09:34 +00:00
Felix DeGrood e7ea5e500f intel/blorp: remove tile flush from emit surface state
Tile cache flush not required when emitting new surface state.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Felix DeGrood c85ea824bc iris: reduce redundant tile cache flushes
We are flushing tile cache more often than is necessary. In
unified cache mode, tile cache flushing is expensive, evicting all
depth/pixel data from the L3$. This is only need for a handful of
cases, such as: making cpu or gpu changes globally visible
(e.g. map), fast color clears, or slow depth clears. Tile cache
flushing is a gen12+ feature.

Remove blanket flushing of tile cache on all depth/RT flushes.
Replace with selective tile cache flushing.

Improves performance in several workloads:
AztecRuins.ogl-high-offscreen-1440p 1%
UnigineValley.ogl-g2                1%
Dota 2 (replay Jul 2020).ogl-g2     1%
Counter-Strike GO.ogl-g2            1%
Manhattan.ogl-Off-19x10             2%
CarChase.ogl-Off-19x10              1%
Bioshock Infinite.ogl-g2            1%

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Kenneth Graunke bfe2c5f667 iris: only flush the render cache for aux changes, not format changes
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Felix DeGrood ed8f2c4cbe iris: Cache VB/IB in L3$ for Gen12
Gen12 enables caching of Vertex and Index Buffers in L3.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Felix DeGrood ed94528711 intel: add L3 Bypass Disable to gen xml
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
2021-04-15 04:54:40 +00:00
Mike Blumenkrantz 376c878c16 mesa/st: plumb GL_TEXTURE_REDUCTION_MODE_ARB through QueryInternalFormat
enable per-format querying of texture_filter_minmax support if the ARB extension
is enabled

also now return 0 if neither extension is supported

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10030>
2021-04-15 01:20:40 +00:00
Mike Blumenkrantz b122beaff3 gallium: split PIPE_CAP_SAMPLER_REDUCTION_MINMAX into modes
this enables detection for the EXT vs the ARB extension, which have
different specifications regarding which formats must be supported

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10030>
2021-04-15 01:20:40 +00:00
Mike Blumenkrantz 59ad872458 gallium: add PIPE_BIND_SAMPLER_REDUCTION_MINMAX
for querying format support

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10030>
2021-04-15 01:20:40 +00:00
Yiwei Zhang 1932207902 venus: implement dma_buf fd import and properties query
This change is for supporting VK_ANDROID_native_buffer implementation,
and it does not advertise VK_KHR_external_memory_fd.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10195>
2021-04-15 00:58:00 +00:00
Yiwei Zhang 001549c92c venus: update venus-protocol headers
Add support for external memory fd properties query and import
- vkGetMemoryResourcePropertiesMESA
- VkImportMemoryResourceInfoMESA
- VkMemoryResourcePropertiesMESA

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10195>
2021-04-15 00:58:00 +00:00
Rob Clark 31782330da freedreno: Add missing foreach macros and update indentation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10247>
2021-04-14 16:53:26 -07:00
Chia-I Wu 9b71154353 venus: remove vn_renderer_info::has_timeline_sync
We are no longer limited to Vulkan 1.1 in VMs.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10146>
2021-04-14 21:18:10 +00:00
Chia-I Wu 37f03a2c4c venus: wait on vkQueuePresentKHR
Add vn_renderer_info::has_implicit_fencing.  Force vkQueueWaitIdle
during vkQueuePresentKHR when it is false.

This kills the performance, but we have to do this until the kernel does
implicit fencing.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10146>
2021-04-14 21:18:10 +00:00