Commit Graph

65371 Commits

Author SHA1 Message Date
Rob Clark 59ff81663a freedreno/ir3: catch incorrect usage of tmp-dst
Each get_dst() should have a matching put_dst().  Add a bit of checking
to catch mistakes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:26:09 -04:00
Ilia Mirkin db1a94b1cc freedreno/ir3: use unsigned comparison for UIF
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:26:05 -04:00
Ilia Mirkin 11d72553c5 freedreno/ir3: negate result of USLT/etc
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:26:01 -04:00
Ilia Mirkin 8edf83b377 freedreno/ir3: add UARL support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:25:57 -04:00
Ilia Mirkin 10273f84c2 freedreno/ir3: INEG operates on src0, not src1
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:25:52 -04:00
Ilia Mirkin 572ffca050 freedreno/ir3: fix FSLT/etc handling to return 0/-1 instead of 0/1.0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:25:47 -04:00
Rob Clark 80058c0f08 freedreno/a3xx: alpha render-target shenanigans
We need the .w component to end up in .x, since the hw appears to fetch
gl_FragColor starting with the .x coordinate regardless of MRT format.
As long as we are doing this, we might as well throw out the remaining
unneeded components.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:23:52 -04:00
Rob Clark 3e0a82b52e util/u_format: add _is_alpha()
Because of render-to-alpha (000x) shenanigans, freedreno needs to do
some special handling when rendering to alpha-only formats.  And I
noticed that while we had _is_luminance(), _is_intensity(), etc, an
_is_alpha() helper was missing.  So fix that.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:23:52 -04:00
Rob Clark 480fe244dd freedreno/a3xx: format fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:23:52 -04:00
Rob Clark 1fba490569 freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:23:52 -04:00
Rob Clark 2ed7640eec freedreno/a3xx: handle rendering to layer != 0
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-12 16:23:52 -04:00
Brian Paul 0d73ac6b02 mesa: fix _mesa_free_pipeline_data() use-after-free bug
Unreference the ctx->_Shader object before we delete all the pipeline
objects in the hash table.  Before, ctx->_Shader could point to freed
memory when _mesa_reference_pipeline_object(ctx, &ctx->_Shader, NULL)
was called.

Fixes crash when exiting the piglit rendezvous_by_location test on
Windows.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-09-12 09:17:31 -06:00
Connor Abbott 2828680e39 ra: assert against unsigned underflow in q_total
q_total should never go below 0 (which is why it's defined as unsigned),
and if it does, then something is seriously wrong.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-12 16:07:47 +02:00
Connor Abbott ec046bc08e ra: note a restriction in the interfence graph API
As noted in the previous commit, this was introduced in
567e2769b8 ("ra: make the p, q test more
efficient"), but I forgot to mention it.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-12 16:07:47 +02:00
Connor Abbott afd82dcad1 r300g: set register classes before interferences
In commit 567e2769b8 ("ra: make the p, q
test more efficient") I unknowingly introduced a new requirement to the
register allocator API: the user must set the register class of all
nodes before setting up their interferences, because
ra_add_conflict_list() now uses the classes of the two interfering
nodes. i965 already did this, but r300g was setting up register classes
interleaved with setting up the interference graph. This led to us
calculating the wrong q total, and in certain cases
e78a01d5e6 (" ra: optimistically color
only one node at a time") made it so that this bug caused a segfault. In
particular, the error occurred if the q total was decremented to 1 below
0 for the last node to be pushed onto the stack.  Since q_total is an
unsigned integer, it overflowed to 0xffffffff, which is what
lowest_q_total happens to be initialzed to. This means that we would
fail the "new_q_total < lowest_q_total" check on line 476 of
register_allocate.c, and so the node would never be pushed onto the
stack, which led to segfaults in ra_select() when we failed to ever give
it a register.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82828
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Pavel Ondračka <pavel.ondracka@email.cz>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-09-12 16:07:07 +02:00
Andreas Boll 2a13ff954d gallium/util: add missing u_debug include
Needed for assert.
Fixes build on BE archs with -Werror=implicit-function-declaration.

In file included from
../../../../../src/gallium/auxiliary/draw/draw_fs.c:30:0:
../../../../../src/gallium/auxiliary/util/u_math.h: In function
'util_memcpy_cpu_to_le32':
../../../../../src/gallium/auxiliary/util/u_math.h:810:4: error:
implicit declaration of function 'assert'
[-Werror=implicit-function-declaration]
    assert(n % 4 == 0);
        ^

Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-12 15:55:12 +02:00
Chia-I Wu 802018df5f ilo: fix builder size checks for BLT buffer clear/copy
In buf_clear_region() and buf_copy_region(), max_cmd_size was set to 0.  If
either of the functions is called and there is not enough space in the
builder, the next ilo_cp_flush() will fail silently in a release build.

Replace magic numbers by size defines in tex_clear_region()/tex_copy_region()
for consistency and readability.
2014-09-12 16:58:31 +08:00
Chia-I Wu 07e0923203 ilo: reduce BLT function parameters
Intruduce gen6_blt_bo and gen6_blt_xy_bo to describe BOs.  In the extreme case
of gen6_XY_SRC_COPY_BLT(), the number of parameters goes down from 18 to 8.
2014-09-12 16:58:30 +08:00
Chia-I Wu 8fa62a9982 ilo: clean up BLT functions
Follow the changes for MI functions, but for BLT this time.
2014-09-12 16:58:30 +08:00
Chia-I Wu a77aaf4363 ilo: clean up MI functions
With ilo_builder in place, some conventions we had to build commands are no
longer needed.
2014-09-12 16:58:30 +08:00
Chia-I Wu 0c6a9cde94 ilo: move BLT functions to ilo_builder_blt.h
Follow the changes for MI functions, but for BLT this time.
2014-09-12 16:58:30 +08:00
Chia-I Wu 50d2d9a69d ilo: move MI functions to ilo_builder_mi.h
Have a centralized place for MI functions, and remove the duplicated
gen6_MI_LOAD_REGISTER_IMM().
2014-09-12 16:58:30 +08:00
Chia-I Wu 521887f9fd ilo: add ILO_DEV_ASSERT()
It replaces ILO_GPE_VALID_GEN().
2014-09-12 16:58:30 +08:00
Chia-I Wu 56d2ebb019 ilo: use an accessor for dev->gen
It should enable us to do specialized builds by making the accessor return a
constant.
2014-09-12 16:58:30 +08:00
Chia-I Wu ea5de3e0bd ilo: add GEN_EXTRACT() and GEN_SHIFT32()
They replace READ() and SET_FIELD() that we have been using.
2014-09-12 16:58:29 +08:00
Chia-I Wu e8f4dd70ab ilo: remove ILO_GEN_GET_MAJOR()
The last user has gone away.
2014-09-12 16:58:29 +08:00
Chia-I Wu 611f09890e ilo: careful with empty fb state in ilo_gpe_set_fb()
We cannot pass 0 as the width or height to ilo_gpe_init_view_surface_null().
2014-09-12 16:58:29 +08:00
Ilia Mirkin 95058bdec3 nv50,nvc0: enable ARB_texture_view
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-09-12 00:57:45 -04:00
Ilia Mirkin d82bd7eb06 mesa/st: add ARB_texture_view support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-09-12 00:55:26 -04:00
Ilia Mirkin c113095acd gallium: add a texture target to sampler view and a CAP to use it
This allows a sampler view to have a different texture target than the
underlying resource. This will be used to implement the type casting
between 2d arrays and cube maps as specified in ARB_texture_view.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-12 00:54:55 -04:00
Ilia Mirkin 3c81de5851 nouveau: only enable stencil func if the visual has stencil bits
The _Enabled property already has the relevant information.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-12 00:51:20 -04:00
Ilia Mirkin 79959e5de5 nouveau: only enable the depth test if there actually is a depth buffer
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-12 00:50:56 -04:00
Maarten Lankhorst 8ab85bfcd5 nouveau: remove unneeded assert
No idea why it was added, but the code runs fine even on videos
where it triggers.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-11 23:18:07 -04:00
Maarten Lankhorst a41aad8431 nouveau: rework reference frame handling
Fixes a regression from "nouveau/vdec: small fixes to h264 handling"

New picking order for frames:
 1. Vidbuf pointer matches.
 2. Take the first kicked ref.
 3. If that fails, take a ref that has a different last_used.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-11 23:18:05 -04:00
Maarten Lankhorst 121ceb38f4 nouveau: fix MPEG4 hw decoding
Reorder some fields to make I-frame decoding work correctly.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-11 23:18:03 -04:00
Maarten Lankhorst f6afed7076 nouveau: re-allocate bo's on overflow
The BSP bo might be too small to contain all of the bsp data,
bump its size on overflow. Also bump inter_bo when this happens,
it might be too small otherwise.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-11 23:17:52 -04:00
Chia-I Wu 1187dbdd10 ilo: fix a compile error with -Werror=format-security
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83777
2014-09-12 09:45:42 +08:00
Ian Romanick 7aeb853c90 i965/vec4: Only examine virtual_grf_end for GRF sources
If the source is not a GRF, it could have a register >= virtual_grf_count.
Accessing virtual_grf_end with such a register would lead to
out-of-bounds access.  Make sure the source is a GRF before accessing
virtual_grf_end.

Fixes Valgrind complaints while compiling some shaders.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2014-09-11 11:18:36 -07:00
Brian Paul a46d7579e9 st/mesa: handle failed context creation for core profile
If the glx/wgl state tracker requested a core profile but the gallium
driver did not support some feature of GL 3.1 or later, we were setting
ctx->Version=0 and then failing the assertion in
_mesa_initialize_exec_table().

With this change we check for ctx->Version=0 and tear down the context
and return NULL from st_create_context().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-11 08:22:55 -06:00
Iago Toral Quiroga f976b4c1bf i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.
So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage.

From ARB_transform_feedback3:

"When a generated primitive query for a vertex stream is active, the
 primitives-generated count is incremented every time a primitive emitted to
 that stream reaches the Discarding Rasterization stage (see Section 3.x)
 right before rasterization. This counter is incremented whether or not
 transform feedback is active."

Unfortunately, we don't have any registers that provide the number of primitives
written to a specific stream other than the ones that track the number of
primitives written to transform feedback in the SOL stage, so we can't
implement this exactly as specified.

In the past we implemented this feature by activating the SOL unit even if
transform feeback was disabled, but making it so that all buffers were
disabled and it only recorded statistics, which gave us the right semantics
(see 3178d2474a). Unfortunately, this came with
a significant performance impact and had to be reverted.

This new take does not intend to implement the exact semantics required by
the spec, but improves what we have now, since now we return the primitive
count for stream 0 in all cases. With this patch we use
GEN7_SO_PRIM_STORAGE_NEEDED to resolve GL_PRIMITIVES_GENERATED queries
for non-zero streams. This would return the number of primitives written
to transform feedback for each stream instead. Since non-zero streams are
only useful in combination with transform feedback this should not be too
bad, and the only case that I think we would not be supporting would be
the one in which we want to use both GL_PRIMITIVES_GENERATED and
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN on the same non-zero stream to
detect buffer overflow.

This patch also fixes the following piglit test:
arb_gpu_shader5-xfb-streams-without-invocations

This test uses both GL_PRIMITIVES_GENERATED and
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries on non-zero streams, but it
does never hit the overflow case, so both queries are always expected to return
the same value.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
2014-09-11 15:17:22 +02:00
Christian König 6327b58415 radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffers
That better matches the actual userspace use case, the
kernel will force it to VRAM if the hardware requires it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:06:09 +02:00
Christian König 4dfdcdb4b3 radeon/video: use the hw to initial clear the buffers
Less CPU overhead and avoids contention over CPU accessible memory on startup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:06:03 +02:00
Christian König 4bc0059229 radeon/video: use more of the common buffer code v2
In preparation to using buffers clears with the hw engine(s).

v2: split out flipping to using hw buffer clears.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:05:55 +02:00
José Fonseca 771ab951a8 scons: add /dynamicbase and /nxcompat to MinGW linkflags
Just like b26503b196d51dc46c815e241343e42ab30e8d66 for MSVC.
2014-09-11 11:59:28 +01:00
Brian Paul 4860e98972 scons: add /dynamicbase and /nxcompat to MSVC linkflags
This builds the opengl DLLs with address layout space randomization
(ASLR) and data execution prevention (DEP) for better security.

Reviewed-by: Kurt Daverman <krd@vmware.com>
2014-09-11 11:59:28 +01:00
Chia-I Wu 6816d853db ilo: add a new disassembler
The old disassembler was modified from i965's.  It is as much work as doing a
new one to keep it up-to-date, which also requires copying more headers over.

The outputs of this new disassembler should match i965's as closely as
possible.
2014-09-11 16:29:38 +08:00
Chia-I Wu b51b349942 ilo: update genhw headers
Add some new registers and some tweaks.  The changes that affect ilo are

 GEN6_REG_HS_INVOCATION_COUNT -> GEN7_REG_HS_INVOCATION_COUNT
 GEN6_REG_DS_INVOCATION_COUNT -> GEN7_REG_DS_INVOCATION_COUNT
 GEN6_COND_NORMAL             -> GEN6_COND_NONE
2014-09-11 16:29:38 +08:00
Frank Henigman 9c707d065a glsl: allow precision qualifier on sampler arrays
If a precision qualifer is allowed on type T, it should be allowed
on an array of T.  Refactor the check to ensure this is the case.

(Fixes failures in WebGL conformance test 'gl-min-textures')

Signed-off-by: Frank Henigman <fjhenigman@google.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-09-11 10:41:00 +03:00
Tapani Pälli 096ee4c3b0 glsl: mark variable as loop constant when it is set read only
Patch modifies is_loop_constant() to take advantage of 'read_only' bit
in ir_variable to detect a loop constant. Variables marked read-only
are loop constant like mentioned by a comment in the function.

v2: remove unnecessary comment (Francisco)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82537
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-09-11 10:09:12 +03:00
Michel Dänzer 82edcb918b radeonsi: Simplify si_dma_copy_tile function
No functional change intended.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-11 12:36:03 +09:00