Commit Graph

145785 Commits

Author SHA1 Message Date
Vadym Shovkoplias 36c241be01 driconf, glsl: Add a vs_position_always_precise option
This is basically the same workaround as in 9b577f2a88 (driconf, glsl: Add a
vs_position_always_invariant option) commit but for tesselation evaluation
shaders. Some applications do not mark outputs as precise in tesselation
evaluation shaders which can lead to different results in case some
optimizations were applied.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Fixes: 09705747d7 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13027>
2021-09-30 10:46:39 +00:00
Boris Brezillon 8276a8eb55 panfrost: Move genxml related files to a subdir
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
2021-09-30 10:30:19 +00:00
Boris Brezillon b76420be1f panfrost: Split command stream descriptor definitions per-gen
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
2021-09-30 10:30:19 +00:00
Boris Brezillon 95b37fd21e panfrost: Add a common genxml file so we can share a few definitions
Start with the enums that were manually redefined in
pan_{texture,format}.h and the blend equation descriptors.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12208>
2021-09-30 10:30:19 +00:00
Samuel Pitoiset 27bb80f688 radv: fix selecting the hash when RADV_FORCE_VRS is enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>
2021-09-30 10:12:43 +00:00
Samuel Pitoiset 0c88c5cdc4 radv: fix adjusting the frag coord when RADV_FORCE_VRS is enabled
force_vrs was always RADV_FORCE_VRS_NONE at that point and the
hw workaround was never applied.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13098>
2021-09-30 10:12:43 +00:00
Samuel Pitoiset dca04dae52 radv: remove the LLVM stat about the number of private VGPRs
This doesn't seem really useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12999>
2021-09-30 09:51:17 +00:00
Daniel Schürmann 7b04c13a34 aco/ra: don't rewrite affinities for phi operands after register assignment
The effect of doing so is random and not meaningful.

Totals from 52 (0.03% of 150170) affected shaders: (GFX10.3)
CodeSize: 538768 -> 538784 (+0.00%); split: -0.04%, +0.04%
Instrs: 100661 -> 100707 (+0.05%); split: -0.01%, +0.06%
Latency: 1205950 -> 1205768 (-0.02%); split: -0.07%, +0.05%
InvThroughput: 200106 -> 200040 (-0.03%); split: -0.31%, +0.28%
Copies: 5717 -> 5754 (+0.65%); split: -0.17%, +0.82%
Branches: 3153 -> 3162 (+0.29%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann b7af10449b aco/ra: create nested affinities for loop header phis
Totals from 875 (0.58% of 150170) affected shaders: (GFX10.3)
CodeSize: 6084528 -> 6066628 (-0.29%); split: -0.32%, +0.02%
Instrs: 1136497 -> 1133565 (-0.26%); split: -0.28%, +0.02%
Latency: 23355051 -> 22952592 (-1.72%); split: -1.83%, +0.10%
InvThroughput: 13028151 -> 12859628 (-1.29%); split: -1.38%, +0.09%
Copies: 85673 -> 82790 (-3.37%); split: -3.62%, +0.26%
Branches: 25049 -> 25098 (+0.20%); split: -0.08%, +0.28%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann d6bfc95732 aco/ra: create affinities between nested phis
Totals from 17143 (11.42% of 150170) affected shaders: (GFX10.3)
VGPRs: 1138112 -> 1138440 (+0.03%); split: -0.00%, +0.03%
CodeSize: 131235532 -> 131147080 (-0.07%); split: -0.14%, +0.07%
Instrs: 24848044 -> 24775419 (-0.29%); split: -0.32%, +0.02%
Latency: 599031816 -> 596005601 (-0.51%); split: -0.52%, +0.01%
InvThroughput: 152059329 -> 151054105 (-0.66%); split: -0.66%, +0.00%
VClause: 410951 -> 410958 (+0.00%); split: -0.01%, +0.01%
Copies: 1696885 -> 1621908 (-4.42%); split: -4.64%, +0.22%
Branches: 846710 -> 851052 (+0.51%); split: -0.29%, +0.80%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann a2ffdca26a aco/ra: don't set affinities for ssa-repair phis
These have no effect anymore.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann ae5cbd8f3a aco/ra: for phis try to find an operand-matching register earlier
Totals from 3557 (2.37% of 150170) affected shaders: (GFX10.3)
VGPRs: 257976 -> 257984 (+0.00%)
CodeSize: 34296232 -> 34270552 (-0.07%); split: -0.09%, +0.01%
Instrs: 6512289 -> 6506900 (-0.08%); split: -0.10%, +0.01%
Latency: 136376181 -> 136262553 (-0.08%); split: -0.10%, +0.02%
InvThroughput: 33042816 -> 32992849 (-0.15%); split: -0.18%, +0.03%
VClause: 104687 -> 104686 (-0.00%)
SClause: 238657 -> 238663 (+0.00%); split: -0.00%, +0.00%
Copies: 477690 -> 471058 (-1.39%); split: -1.52%, +0.13%
Branches: 223058 -> 224326 (+0.57%); split: -0.02%, +0.59%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 8995599c80 aco/ra: try more aggressive to assign phi defs the same register
Totals from 4158 (2.77% of 150170) affected shaders: (GFX10.3)
VGPRs: 312008 -> 312000 (-0.00%)
CodeSize: 42902064 -> 42892200 (-0.02%); split: -0.06%, +0.04%
Instrs: 8086443 -> 8084532 (-0.02%); split: -0.07%, +0.05%
Latency: 138551153 -> 138215222 (-0.24%); split: -0.28%, +0.03%
InvThroughput: 39676773 -> 39570850 (-0.27%); split: -0.29%, +0.02%
SClause: 306299 -> 306284 (-0.00%); split: -0.01%, +0.00%
Copies: 552481 -> 553353 (+0.16%); split: -0.75%, +0.91%
Branches: 284381 -> 282409 (-0.69%); split: -0.74%, +0.04%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 28fe49c35f aco/ra: split register assignment for phis into separate function
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 302cb5c900 aco/ra: remove some redundant code
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann d7cb169819 aco/ra: refactor affinities into assignment struct
This lets us get rid of an unordered_map<>.

No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Daniel Schürmann 5afcc17f50 aco/ra: fix intersects()
The previous implementation failed when a contained b.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12836>
2021-09-30 09:10:07 +00:00
Samuel Pitoiset 9ea0351660 radv: fix missing features for BDA
Only the KHR one is filled by the common code.

Fixes: ec2007d47e ("radv: Use the shared now-in-core feature/prop extension helper functions.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13035>
2021-09-30 08:51:57 +00:00
Jason Ekstrand d2264489ce compiler/clc: grab opencl-c.h from the system path by default
By default we use the header installed opencl-c.h header. But in the
case Mesa is compiled for microsoft clon12 we keep the injected file.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Jason Ekstrand 8490766f53 compiler/clc: Clean ups
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Jason Ekstrand 1506ea2ecb Move a bunch of the CLC stuff from src/microsoft to common code
The D3D12-specific stuff isn't useful to have in common code but all the
stuff to invoke clang really should be common.

v2: Rebase (Lionel)

v3: Define a new clc_libclc_new_dxil() entrypoint to create a clc
    context with DXIL nir_options (Jesse)

v4: Fixup meson build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Lionel Landwerlin a9c49a0541 meson: extract libversion checks from clc & clover
The src/microsoft/clc/meson.build was assuming to be run only on
Windows. That's about to change.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Lionel Landwerlin 2bc4650b45 microsoft/clc: fix compiler warning on uninitiailzed variable use
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Lionel Landwerlin 1d7a5196b1 microsoft/clc: drop MSVC specific function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
2021-09-30 07:09:08 +00:00
Stéphane Marchesin dd5bf189ef virgl: Flush context before waiting on fences
The logic behind this change is intuitive: if we are waiting for
something, we should probably flush all pending rendering so that it
starts executing in the meantime. This prevents the GPU from sitting
idle for long periods of time while we are also blocked in the app.

With the gun3d trace:
Before: 79 fps After: 215 fps

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13096>
2021-09-30 04:40:56 +00:00
Yiwei Zhang 7c22ece8e4 util: fix sign comparison
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13074>
2021-09-30 04:19:27 +00:00
Jason Ekstrand 709e187003 st/texture: Fall back to single-slice uploads in st_CompressedTexSubImage
Currently, if we ever fail to create a re-interpreted uncompressed view
of the resource, we fall back to a SW path.  On some Intel hardware,
this happens whenever LOD > 0.  Instead, we should fall back to
attempting to upload one slice at a time and only fall back to SW as a
last resort.

v2 [by Ken]: Fix buf_offset calculation and loop over layers.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11737>
2021-09-30 03:52:33 +00:00
Jason Ekstrand b7ab625ea9 st/texture: Dedent surface setup in CompressedTexSubImage
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11737>
2021-09-30 03:52:33 +00:00
Qiang Yu e55e61758c loader/dri3: fix swap out of order when changing swap interval
This fixes SPECVIEWPERF13 creo test case hang:
  1. Client: send present pixmap request (serial=1) when swap_interval==1
     and increase send_sbc=1
  2. Server: pend the request before vblank arrives
  3. Client: set swap_interval=0 (so set XCB_PRESENT_OPTION_ASYNC),
     send another present pixmap request (serial=2), increase send_sbc=2
  4. Server: handle the async request immediately and send complete event
     (serial=2)
  5. Client: handle the event and set recv_sbc=event->serial=2
  6. Server: vblank arrives so handle pending request and send complete
     event (serial=1)
  7. Client: handle the event and set recv_sbc=event->serial=1
  8. Client: someone call loader_dri3_swapbuffer_barrier() and waiting
     on recv_sbc==send_sbc, but no one will set recv_sbc=2 again

So basically it's caused by swap happens out of order. This commit
fixes the problem by waiting on the pending sync swaps all done when
switching to async mode, so move 6&7 before 3.

Attach the xtrace when problem happens:

  005:<:003e: 72: Present-Request(148,1): Pixmap window=0x03000002 pixmap=0x0300000b serial=1 valid=0x00000000 update=0x00000000 x_off=0 y_off=0 target_crtc=0x00000000 wait_fence=0x00000000 idle_fence=0x0300000c options=0 target_msc=4294967296 divisor=0 remainder=0 notifies=;
  ...
  005:<:0041: 72: Present-Request(148,1): Pixmap window=0x03000002 pixmap=0x03000011 serial=2 valid=0x00000000 update=0x00000000 x_off=0 y_off=0 target_crtc=0x00000000 wait_fence=0x00000000 idle_fence=0x03000012 options=Async target_msc=0 divisor=0 remainder=0 notifies=;
  005:>:0041: Event Generic(35) Present(148) IdleNotify(2) event=0x03000006 window=0x03000002 serial=2 pixmap=0x03000011 idle_fence=0x03000012
  005:>:0041: Event Generic(35) Present(148) CompleteNotify(1) kind=Pixmap(0x00) mode=Copy(0x00) event=0x03000006 window=0x03000002 serial=2 ust=7505462213117739011 msc=3565046193979392
  005:>:0041: Event Generic(35) Present(148) IdleNotify(2) event=0x03000006 window=0x03000002 serial=1 pixmap=0x0300000b idle_fence=0x0300000c
  005:>:0041: Event Generic(35) Present(148) CompleteNotify(1) kind=Pixmap(0x00) mode=Copy(0x00) event=0x03000006 window=0x03000002 serial=1 ust=7505533793042694147 msc=3565050488946688

Cc: mesa-stable
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13019>
2021-09-30 03:27:14 +00:00
Chia-I Wu 443bf16782 venus: keep layouts of descriptor sets alive
We might reorder vkCmdBindDescriptorSets after
vkDestroyDescriptorSetLayout due to batching, which is likely invalid.
Keep the layouts alive with the sets to defer
vkDestroyDescriptorSetLayout.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>
2021-09-30 03:16:19 +00:00
Chia-I Wu e88c7191aa venus: add vn_refcount to vn_descriptor_set_layout
The reference count does not go beyond 1 yet.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>
2021-09-30 03:16:19 +00:00
Chia-I Wu 5337fb1e06 venus: add a helper to destroy vn_descriptor_set
Add vn_descriptor_set_destroy.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>
2021-09-30 03:16:19 +00:00
Chia-I Wu d7560a71a2 venus: convert bo and shmem to use vn_refcount
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>
2021-09-30 03:16:19 +00:00
Chia-I Wu 5cdbf75615 venus: add vn_refcount
Memory ordering is hard.  Add vn_refcount to take care of the details.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13090>
2021-09-30 03:16:19 +00:00
Jason Ekstrand 1da70c7e93 v3dv: Use VK_DEFINE_*HANDLE_CASTS instead of rolling our own
The core ones have some nifty stuff like asserts that it's a valid
vk_object_base and has the right type.  We don't have real type safety
with Vulkan handles but this is as close as we can get.  The core ones
also track when we've started handing out handles for logging purposes
which we want.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13101>
2021-09-29 23:27:52 +00:00
Jason Ekstrand 24637a6579 vulkan/shader_module: Fix the lifetime of temporary shader modules
The vk_shader_module_handle_from_nir() macro was constructing a
temporary vk_shader_module and passing it through
vk_shader_module_to_handle().  Since this is a function and not a macro,
it means that the lifetime of the temporary vk_shader_module will end
once the to_handle() function is called.  Technically, this is a
use-after-free.  I really don't know why no one has been bitten by this
yet....

Fixes: a41e98ddca "vk/util: add a util macro for initializing stack..."
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13101>
2021-09-29 23:27:52 +00:00
Rob Clark 2b826582d8 isaspec: De-duplicate bitset encoding
bitset encoding tends to have a lot of duplication, for ex. many
instructions with the same encoding modulo the fixed pattern.  Now that
encode_bitset is split out into it's own template, so that we can
capture the result, use a hash table to de-duplicate the bitset encoding
into "snippet" functions so that bitset cases with identical encoding
can re-use the same generated code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
2021-09-29 22:59:43 +00:00
Rob Clark 8726ed7221 isaspec: Split encode_bitset() into it's own template
In the next patch, we are going to want to be able to capture the result
of rendering the template as a py variable, which I don't think you can
do otherwise with a <%def>.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
2021-09-29 22:59:43 +00:00
Rob Clark 72db4e51f3 isaspec: Fix comment
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
2021-09-29 22:59:43 +00:00
Rob Clark cd3ee83ca5 isaspec: Remove unused leftovers
These were never used, leftovers from an earlier iteration of isaspec
which used an RPN based thing for expressions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
2021-09-29 22:59:43 +00:00
Dylan Baker 878cc65c40 docs: update calendar and link releases notes for 21.2.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13109>
2021-09-29 22:53:32 +00:00
Dylan Baker 56510179b6 docs" Add SHA256 sum for mesa 21.2.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13109>
2021-09-29 22:53:32 +00:00
Dylan Baker 4423581ab3 docs: add release notes for 21.2.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13109>
2021-09-29 22:53:32 +00:00
Chia-I Wu a3f2ffcc02 venus: copy VkPhysicalDeviceImageDrmFormatModifierInfoEXT
We should not drop VkPhysicalDeviceImageDrmFormatModifierInfoEXT when it
is provided.

Fixes dEQP-VK.drm_format_modifiers.export_import.*.

Fixes: efa185ed5c ("venus: rework external memory capability queries")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13094>
2021-09-29 22:41:01 +00:00
Dave Airlie b9aee98912 gallivm: use pmulhrsw to make aos sampling more accurate.
This uses pmulhrsw avx2 and ssse3 variants. It fixes the
precision of texture filtering calculations.

However it does leave these paths inaccurate on platforms
that don't support it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13075>
2021-09-29 21:55:23 +00:00
Rhys Perry 2f0a007976 radv: workaround incorrect image format with World War Z
The image format in a FSR-related shader is incorrect.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5407
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13084>
2021-09-29 21:13:15 +00:00
Jason Ekstrand 0737b37dcd intel/fs: Emit URB fences when we have LSC
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
2021-09-29 20:52:54 +00:00
Jason Ekstrand e6a9501aa2 intel/fs: Add the URB fence message
When they re-arranged all the dataport stuff and added the LSC, doing
URB fencing through the dataport no longer makes sense.  Instead, there
is now a fence message on the URB shared function.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
2021-09-29 20:52:54 +00:00
Jason Ekstrand eb53d82d2d intel/fs: Ignore SLM fences if shared is unused
Found this nugget while looking at the ACO driver.  It seems sensible to
avoid SLM fences if there is no SLM.  This also makes the check depend
on SLM usage rather than just shader stage which will be useful if we
ever implement task/mesh because task shaders also have SLM.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
2021-09-29 20:52:54 +00:00
Jason Ekstrand f726246297 intel/fs: Rework fence handling in brw_fs_nir.cpp
Start off making everything look like LSC where we have three types of
fences: TGM, UGM, and SLM.  Then, emit the actual code in a generation-
aware way.  There are three HW generation cases we care about:
XeHP+ (LSC), ICL-TGL, and IVB-SKL.  Even though it looks like there's a
lot to deduplicate, it only increases the number of ubld.emit() calls
from 5 to 7 and entirely gets rid of the SFID juggling and other
weirdness we've introduced along the way to make those cases "general".
While we're here, also clean up the code for stalling after fences and
clearly document every case where we insert a stall.

There are only three known functional changes from this commit:

 1. We now avoid the render cache fence on IVB if we don't need image
    barriers.

 2. On ICL+, we no longer unconditionally stall on barriers.  We still
    stall if we have more than one to help tie them together but
    independent barriers are independent.  Barrier instructions will
    still operate in write-commit mode and still be scheduling barriers
    but won't necessarily stall.

 3. We now assert-fail for URB fences on LSC platforms.  We'll be adding
    in the new URB fence message for those platforms in a follow-on
    commit.

It is a big enough refactor, however, that other minor changes may be
present.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
2021-09-29 20:52:54 +00:00