Commit Graph

63965 Commits

Author SHA1 Message Date
Roland Scheidegger 188ba1d6ec target-helpers: don't use designated initializers
it looks since ce1a137228 they are now included
in more places, in particular even for things buildable with msvc, and hence
those break the build.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-07-02 01:55:59 +02:00
Christoph Bumiller b97b87940b st/mesa: add support for indirect drawing 2014-07-02 00:47:10 +02:00
Marek Olšák 59330f13b0 gallium/u_vbuf: get draw info from an indirect buffer if there's any
This is required for fallbacks to work with ARB_draw_indirect.
2014-07-02 00:47:10 +02:00
Christoph Bumiller bc198f8e63 gallium: add facilities for indirect drawing
v2:
Added comments to util_draw_indirect, clarified and fixed map size.
Removed unlikely().
2014-07-02 00:47:09 +02:00
Christoph Bumiller a27b3582a6 gallium: add PIPE_BIND_COMMAND_ARGS_BUFFER
Intended for use with GL_ARB_draw_indirect's DRAW_INDIRECT_BUFFER
target or for D3D11_RESOURCE_MISC_DRAWINDIRECT_ARGS.
2014-07-02 00:47:09 +02:00
Dave Airlie 8392179fcc xmlconfig/dri: bool -> unsigned char
Drop stdbool, due to the X server being a pain and having
struct members called bool, although I've sent a patch to fix
that we should retain stupidity here. Use unsigned char
which is what GLboolean is anyways.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-07-02 08:24:05 +10:00
Cody Northrop 78121e4b8d i965/fs: Update discard jump to preserve uniform loads via sampler.
Commit 17c7ead7 exposed a bug in how uniform loading happens in the
presence of discard.  It manifested itself in an application as
randomly incorrect pixels on the borders of conditional areas.

This is due to how discards jump to the end of the shader incorrectly
for some channels.  The current implementation checks each 2x2
subspan to preserve derivatives.  When uniform loading via samplers
was turned on, it uses a full execution mask, as stated in
lower_uniform_pull_constant_loads(), and only populates four channels
of the destination (see generate_uniform_pull_constant_load_gen7()).
It happens incorrectly when the first subspan has been jumped over.

The series that implemented this optimization was done before the
changes to use samplers for uniform loads.  Uniform sampler loads
use special execution masks and only populate four channels, so we
can't jump over those or corruption ensues.

This fix only jumps to the end of the shader if all relevant channels
are disabled, i.e. all 8 or 16, depending on dispatch.  This
preserves the original GLbenchmark 2.7 speedup noted in commit
beafced2.

It changes the shader assembly accordingly:

before   : (-f0.1.any4h)  halt(8)  17 2  null { align1 WE_all 1Q };
after(8) : (-f0.1.any8h)  halt(8)  17 2  null { align1 WE_all 1Q };
after(16): (-f0.1.any16h) halt(16) 17 2  null { align1 WE_all 1H };

v2: Cleaned up comments and conditional ordering.
v3: Fix typo.

Signed-off-by: Cody Northrop <cody@lunarg.com>
Reviewed-by: Mike Stroyan <mike@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79948
2014-07-01 13:22:28 -07:00
Matt Turner fcac7020cf i965/fs: Mark case unreachable to silence warning.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:52 -07:00
Matt Turner 3d826729da i965: Use unreachable() instead of unconditional assert().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:52 -07:00
Matt Turner a3d10c2c30 mesa: Make unreachable macro take a string argument.
To aid in debugging.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:52 -07:00
Matt Turner e658440234 i965/vec4: Remove useless conditionals.
Setting a couple of bits is the same cost or less as conditionally
setting a couple of bits.
2014-07-01 08:55:52 -07:00
Matt Turner 2e90d1fb62 i965/fs: Pass cfg to calculate_live_intervals().
We've often created the CFG immediately before, so use it when
available.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:52 -07:00
Matt Turner ec1b2d6aa0 i965: Mark fields in the live interval classes protected.
cfg, for instance, is a pointer to a local variable in
calculate_live_intervals, certainly not valid after that function has
returned.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:52 -07:00
Matt Turner 021094481c glsl: Remove now unused foreach_list* macros.
foreach_list_typed_const was never used as far as I can tell.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:52 -07:00
Matt Turner 266109736a i965: Use typed foreach_in_list_safe instead of foreach_list_safe.
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner c5030ac0ac i965: Use typed foreach_in_list instead of foreach_list.
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner bc2fbbafd2 i965: Add and use foreach_inst_in_block macros.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner e8e5f0a342 i965/fs: Use is_head_sentinel() instead of ->prev == NULL.
Makes it more clear what we're doing and requires less knowledge of
exec_list.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner d6bb8bb7ce mesa: Add and use foreach_list_typed_safe.
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner 22cd917329 mesa: Add and use foreach_in_list_use_after.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner d49173a97b glsl: Replace uses of foreach_list_const.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner fd8f65498a glsl: Replace another couple uses of foreach_list.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner 6e217ad1d7 glsl: Use foreach_list_typed when possible.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner 373824d769 mesa: Use typed foreach_in_list_safe instead of foreach_list_safe.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner c6a16f6d0e glsl: Use typed foreach_in_list_safe instead of foreach_list_safe.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner e0cb82d0c4 mesa: Use typed foreach_in_list instead of foreach_list.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner 4d78446d78 glsl: Use typed foreach_in_list instead of foreach_list.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner da9f0316e6 glsl: Add typed foreach_in_list_safe macro.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Matt Turner 3597681040 glsl: Add typed foreach_in_list/_reverse macros.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-07-01 08:55:51 -07:00
Axel Davy 4d6c9352f3 mesa: fix the condition in src/loader/Makefile.am
We want to have the dri common files compiled to define USE_DRICONF.
We need to check both NEED_OPENGL_COMMON and HAVE_DRICOMMON

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Tested-by: Brian Paul <brianp@vmware.com>
2014-07-01 09:42:44 -06:00
Brian Paul ad6e1e12cc mesa: update comment for UniformBufferSize to indicate size is in bytes
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 09:42:44 -06:00
Brian Paul f4b0ab7afd st/mesa: fix incorrect size of UBO declarations
UniformBufferSize is in bytes so we need to divide by 16 to get the
number of constant buffer slots.  Also, the ureg_DECL_constant2D()
function takes first..last parameters so we need to subtract one
for the last value.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 09:42:44 -06:00
Brian Paul 01bf8bb875 st/mesa: don't use address register for constant-indexed ir_binop_ubo_load
Before, we were always using the address register and indirect addressing
to index into a UBO constant buffer.  With this change we only do that
when necessary.

Using the piglit bin/arb_uniform_buffer_object-rendering test as an
example:

Shader code:
  uniform ub_rot {float rotation; };
  ...
  m[1][1] = cos(rotation);

Before:
  IMM[1] INT32 {0, 1, 0, 0}
  1: UARL ADDR[0].x, IMM[1].xxxx
  2: MOV TEMP[0].x, CONST[3][ADDR[0].x].xxxx
  3: COS TEMP[1].x, TEMP[0].xxxx

After:
  0: COS TEMP[0].x, CONST[3][0].xxxx

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 09:42:44 -06:00
Brian Paul dfca35f807 st/mesa: allow 2D indexing for all shader types in translate_src()
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 09:42:44 -06:00
Brian Paul f11e3dc122 st/mesa: don't ignore const buf index in src_register()
Otherwise, if we were creating a const buffer src register for a UBO
the index into the UBO was always zero.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 09:42:44 -06:00
Ilia Mirkin 5e04526399 nvc0: expose 4 vertex streams, use stream ids in xfb
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-07-01 11:34:40 -04:00
Ilia Mirkin 2f2467cb23 nvc0/ir: only merge emit/restart for identical streams
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-07-01 11:34:40 -04:00
Ilia Mirkin e5cdbdecd2 nvc0/ir: avoid creating restarts with non-0 stream
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-07-01 11:34:40 -04:00
Ilia Mirkin 40b8aec251 nvc0/ir: fix emitting vertex stream
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-07-01 11:34:40 -04:00
Ilia Mirkin 1d16dbf416 mesa/st: add vertex stream support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 11:34:37 -04:00
Ilia Mirkin 746e5260f6 gallium: add a cap for max vertex streams
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 11:34:35 -04:00
Ilia Mirkin 43e4b3e311 gallium: add an index argument to create_query
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 11:34:31 -04:00
Ilia Mirkin 7f1b365f65 gallium: add support for stream in so info
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 11:34:28 -04:00
Ilia Mirkin 0cbefc1bea gallium: add vertex stream argument to EMIT/ENDPRIM
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-01 11:34:24 -04:00
Matt Turner 1bfc0a1102 i965/fs: Mark predicated PLN instructions with dependency hints.
To implement the unlit_centroid_workaround, previously we emitted

   (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q };
   (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q };

where the flag register contains the channel enable bits from g0.

Since the predicates are complementary, the pair of pln instructions
write to non-overlapping components of the destination, which is the
case that the dependency control hints are designed for.

Typically setting dependency control hints on predicated instructions
isn't safe (if an instruction doesn't execute due to the predicate, it
won't update the scoreboard, leaving it in a bad state) but since we
must have at least one channel executing (i.e., +f0 is true for some
channel) by virtue of the fact that the thread is running, we can put
the +f0 pln instruction last and set the hints:

   (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q };
   (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q };

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-30 22:31:06 -07:00
Matt Turner 4fe53ee5d7 i965/fs: Predicate PLN instructions used in unlit centroid WA.
Maybe lets us skip some PLN instructions if whole subspans are disabled?

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-30 22:31:05 -07:00
Matt Turner 6d2536395d i965/fs: Add no_dd_{clear,check} fields to fs_inst.
And plumb them through. Also make the assert in the generator look like
the vec4 one.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-30 22:31:05 -07:00
Matt Turner bcbb7c41b7 i965/fs: Let sat-prop ignore live ranges if producer already has sat.
This sequence (where both x and w are used afterwards) wasn't handled.

   mul.sat x, y, z
   ...
   mov.sat w, x

We assumed that if x was used after the mov.sat, that we couldn't
propagate the saturate modifier, but in fact x was already saturated.

So ignore the live range check if the producing instruction already
saturates its result. Cuts one instruction from hundreds of TF2 shaders.

total instructions in shared programs: 1995631 -> 1994951 (-0.03%)
instructions in affected programs:     155248 -> 154568 (-0.44%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-30 22:31:05 -07:00
Matt Turner e58992aedd i965/fs: Pass const references to emit functions.
Cuts 10k of .text and saves a bunch of useless struct copies.
2014-06-30 22:31:05 -07:00
Matt Turner 35b741c8e7 i965/vec4: Pass const references to instruction functions.
text	   data	    bss	    dec	    hex	filename
4231165	 123200	  39648	4394013	 430c1d	i965_dri.so
4186277	 123200	  39648	4349125	 425cc5	i965_dri.so

Cuts 43k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-30 22:31:05 -07:00