Commit Graph

105048 Commits

Author SHA1 Message Date
Gabriel Majeri f0b987646a anv: Ensure discreteQueuePriorities is at least 2
This is the minimum value according to the spec.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-10-03 07:57:37 +02:00
Timothy Arceri 2b5f42068d r600: use build-id when available for disk cache
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Timothy Arceri 397f2603eb nouveau: use build-id when available for disk cache
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Timothy Arceri 2169acbf34 radeonsi: use build-id when available for disk cache
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Timothy Arceri 83ea8dd99b util: add disk_cache_get_function_identifier()
This can be used as a drop in replacement for
disk_cache_get_function_timestamp().

Here we use build-id to generate a driver-id rather than build
timestamp if available. This should resolve issues such as
distros using reproducable builds and flatpak not having
real build timestamps.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Timothy Arceri 6a884014e4 util: rename timestamp param in disk_cache_create()
Only some drivers use a timestamp here. Others use things such
as build-id, or even a combination of build-ids from Mesa and
LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-03 09:49:21 +10:00
Józef Kucia e24a4e05c7 radeonsi: avoid sending GS_EMIT in shaders without outputs
Fixes GPU hangs.

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107857
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-02 17:13:52 -04:00
Fritz Koenig 08f97407fb i965: Replace checks for rb->Name with FlipY (v2)
In the GL_MESA_framebuffer_flip_y implementation
_mesa_is_winsys_fbo checks were replaced with
FlipY checks.  rb->Name is also used to determine
if a buffer is winsys.

v2: Fixes annotation [for emil]

Fixes: ab05dd183c ("i965: implement GL_MESA_framebuffer_flip_y [v3]")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2018-10-02 11:28:46 -07:00
Marek Olšák 2fd58d8eb2 radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILY
so that it's not NULL when loading radeonsi and a GCN GPU is not
present in the system.
2018-10-02 12:21:49 -04:00
Marek Olšák 0b062f0419 radeonsi: don't set the VS prolog key for the blit VS 2018-10-02 12:21:49 -04:00
Jason Ekstrand 58360ca09d spirv: Move function call handling to vtn_cfg
It makes way more sense for it to live there with the rest of function
handling.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-10-02 10:24:56 -05:00
Jason Ekstrand 00f385e6d4 nir/from_ssa: Don't rewrite derefs destinations to registers
We already call nir_rematerialize_derefs_in_use_blocks_impl prior to
calling nir_lower_ssa_defs_to_regs_block so the assertion that all deref
uses in the block should hold.  This fixes the following CTS test when
SPIR-V optimization recipe 1:

dEQP-VK.glsl.struct.local.loop_nested_struct_array_vertex

Fixes: 606eb56ab9 "intel/nir: Only lower load/store derefs"
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-10-02 10:24:56 -05:00
Jason Ekstrand bfc89c668e nir/cf: Remove phi sources if needed in nir_handle_add_jump
If the block in which the jump is inserted is the predecessor of a phi
then we need to remove phi sources otherwise the phi may end up with
things improperly connected.  This fixes the following CTS test when
dEQP is run with SPIR-V optimization recipe 1:

dEQP-VK.glsl.functions.control_flow.return_in_nested_loop_vertex

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-10-02 10:24:56 -05:00
Eric Engestrom 7b0752fb10 anv: suppress warning about unhandled image layout
Let's just be explicit that VK_NV_shading_rate_image is not supported.

Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>
Fixes: 6ee1709170 "vulkan: Update the XML and headers to 1.1.86"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2018-10-02 15:09:29 +01:00
Rob Clark ae78489d3e freedreno/a6xx: hwbinning
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-02 10:08:18 -04:00
Rob Clark 8ff349e564 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-02 10:08:18 -04:00
Jason Ekstrand 7e7959fcb7 intel/fs: Fix a typo in need_matching_subreg_offset
This fixes a bunch of Vulkan subgroup tests on little core platforms.

Fixes: 4150920b95 "intel/fs: Add a helper for emitting scan operations"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-02 07:44:25 -05:00
Timothy Arceri ea66bfda88 util: disable cache if we have no build-id and timestamp is zero
Timestamp can be zero for example when Flatpak is used. In this
case just disable the cache rather then segfaulting when
incompatible cache items are loaded.

V2: actually return false when mtime is 0.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-02 22:07:55 +10:00
Eric Engestrom 0bdf7b1d0f include: sync eglext.h from Khronos
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
2018-10-02 12:10:46 +01:00
Timothy Arceri 0e6cdfd561 radeonsi: add a workaround for bitfield_extract when count is 0
This ports the fix from 3d41757788. Both LLVM 7 & 8 continue
to have this problem.

It fixes rendering issues in some menu and loading screens of
Civ VI which can be seen in the trace from bug 104602.

Note: This does not fix the black triangles on Vega for bug
104602.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
2018-10-02 08:39:51 +10:00
Jason Ekstrand e4538b93f5 anv: Implement VK_KHR_driver_properties
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 13:21:12 -05:00
Jason Ekstrand 6ee1709170 vulkan: Update the XML and headers to 1.1.86
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 11:43:20 -05:00
Samuel Pitoiset c2867e4c2a radv: do not try to set DCC_CONTROL when image doesn't use DCC
Unnecessary. While we are at it, remove the check for pre-VI
because it's already checked earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 12:13:12 +02:00
Samuel Pitoiset f622ab889a radv: add a sanity check for mutable formats and TC-compat HTILE
If apps use the MUTABLE bit and the same formats as the image one
in the list, we can still enable TC-compat HTILE. I don't think
this happens often but given the fact that TC-compat HTILE allows
a nice boost in some situations, it's worth checking.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 12:13:09 +02:00
Samuel Pitoiset dc91c4d40a radv: disable HTILE for very small depth surfaces
Like we disable DCC/CMASK for small color surfaces as well.
Serious Sam 2017 creates a 1x1 depth surface and I think
it should be faster to do slow clears on the graphics queue
instead of fast clears on compute, and eventually a depth
expand if the surface isn't TC-compatible HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 10:16:33 +02:00
Samuel Pitoiset 6cfa321c39 radv: add potential missing fields for DB_EQAA
Other drivers set these two as well, just apply the same rule.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 10:16:30 +02:00
Samuel Pitoiset bd6df2f923 radv: disable complicated point clipping against user clip planes
I don't think this is required by Vulkan too.

Ported from RadeonSI (AMDVLK doesn't set it either).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-01 10:16:25 +02:00
Michel Dänzer cb863de626 gallium/util: Clarify comment in util_init_thread_pinning
As discussed in the review of the patch which added the comment:

Nothing happens when a thread is created, because pthread_atfork doesn't
affect creating threads. However, spawning a child process will likely
crash.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-09-28 17:52:11 +02:00
Samuel Pitoiset 3fb4adae83 radv: do not sync CP DMA when copying buffers
We already track if the DMA engine is busy/idle with a flag,
and we emit a packet that waits for all CP DMA operations
to be complete. This is done at end of command buffer because
the kernel doesn't wait for them, and also when emitting
barriers, so it should be safe.

This improves small copies for both aligned and unaligned sizes.

Aligned sizes:
BEFORE:
1 KB: 59.840000 ms
2 KB: 71.200000 ms
AFTER:
1 KB: 31.200000 ms
2 KB: 31.040000 ms

Unaligned sizes:
BEFORE:
2 KB: 68.3200 ms
3 KB: 79.3600 ms
5 KB: 76.6400 ms
9 KB: 90.8800 ms
17 KB: 116.0000 ms
AFTER:
2 KB: 31.0400 ms
3 KB: 32.0000 ms
5 KB: 30.8800 ms
9 KB: 30.5600 ms
17 KB: 29.6000 ms

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-28 09:08:52 +02:00
Samuel Pitoiset 621e70dd40 radv: adjust the CmdUpdateBuffer threshold for optimal performance
According to my benchmark results, it appears that we should
reduce the threshold to 1024.

BEFORE:
1 KB: 68.656000 ms
2 KB: 118.368000 ms

AFTER:
1 KB: 31.760000 ms
2 KB: 29.840000 ms

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-28 09:08:44 +02:00
Samuel Pitoiset 5d6a560a29 radv: do not use the availability bit for timestamp queries
It's unnecessary because we can just check if the timestamp
is to different to the default value when a pool is created
or resetted. Instead of waiting for the availability bit to
be 1, we have to emit a not equal WAIT_REG_MEM for checking
if the timestamp is ready.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-09-28 09:08:03 +02:00
Kristian H. Kristensen 3e90505224 freedreno/a6xx: Build up draw dword0 outside visibilty if statement
Pulling this logic out means we can share the logic and avoid a couple
of temporary variables that helped make things clearer before. Note
that in either vismode case, we always program vismode 0.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Kristian H. Kristensen 74a87cdaa6 freedreno/a6xx: Simplify draw_emit() branches a bit
Now that we've copied the emit logic into each branch of the
if (info->index_size) statement, we can simplify the logic a bit
according to which case we're in.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Kristian H. Kristensen 2516073cb6 freedreno/a6xx: Copy OUT_RING() part into each branch of the index if
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Kristian H. Kristensen c3d58d9ffc freedreno/a6xx: Split fd6_draw_emit into direct and indirect paths
This splits the two code paths into separate functions and moves the
"if (info->indirect)" test into draw_impl().

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Kristian H. Kristensen adcd83fb22 freedreno/a6xx: Inline fd6_draw()
Simplify the code a bit by inlining this helper.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Kristian H. Kristensen fb1c6b89a2 freedreno/a6xx: Move emit_marker and wfi to draw_impl()
This way the markers clearly bracket the draw call and isn't
duplicated for both direct and indirect draw code.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Kristian H. Kristensen 0559050557 freedreno/a6xx: Move inline functions out of fd6_draw.h
Only used in fd6_draw.c so put them there.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-09-27 16:08:52 -04:00
Hyunjun Ko 1a40faa864 freedreno: fix a typo in launch_grid 2018-09-27 16:06:19 -04:00
Hyunjun Ko aef410f31e freedreno/ir3: fix the param order of cmpxchg
According to the following definition,
int AtomicCompSwap(inout int mem, uint compare, uint data);

the preceding one in atomic_comp_swap of NIR is compare and data is
followed, while src0 for cmpxchg needs vec2(data, compare)
So for ssbo/image deref comp_swap, that should be reversed.

Fixes: dEQP-GLES31.functional.image_load_store.*.atomic.comp_swap*
2018-09-27 16:05:49 -04:00
Rob Clark 49d22c2dfc freedreno/a6xx: fix shaders w/ >= 24 regs
Possibly these bits mean something else now.  Blob always seems to use
FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads
to overlap registers.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:49:14 -04:00
Rob Clark 6530fcc4a7 freedreno/a6xx: fix gl_FragCoord.w
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:45:44 -04:00
Rob Clark 919741b8d5 freedreno: handle invalidated buffers harder
Do a better job of skipping mem2gmem/gmem2mem..

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:41:46 -04:00
Rob Clark 19e9d28646 freedreno/a6xx: fix constlen
Fix a few bits of confusion, as with previous gen's constlen is aligned
to 4, and value in bitfield is left-shifted by 2 (ie. divided by 4).
But this is done by the CONSTLEN() accessor/builder fxn, so don't do it
twice.  Also HLSQ_FS_CNTL.CONSTLEN is not special.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:33:10 -04:00
Rob Clark 12de415ad1 freedreno: fix inorder rendering case
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:32:39 -04:00
Rob Clark b65b6f7606 freedreno/a6xx: backface stencil state
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:31:56 -04:00
Rob Clark 93db15d300 freedreno/a6xx: fix gpu crash with separate-stencil
Fixes a crash in (of all things) dEQP-GLES2.info.vendor with
--deqp-surface-type=fbo..

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:31:34 -04:00
Rob Clark a52ef80d24 freedreno/a6xx: fix MRT config
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:30:36 -04:00
Rob Clark 8930e83642 freedreno: fix potential hang when destroying batch
batch_flush_reset_dependencies() expects to be called unlocked, and can
call fd_batch_reference() which can try to aquire the screen lock again.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:29:45 -04:00
Rob Clark ef6d15f8a8 freedreno: fix corrupted fb state
In c3d9f29b we allowed ctx->batch to be null, and started tracking the
current framebuffer state in fd_context.  But the existing logic in
fd_blitter_pipe_begin() would, if !ctx->batch, set null fb state to be
restored after blit.  Which broke the world of deqp (and probably other
things)

Fixes: c3d9f29b78 freedreno: allocate ctx's batch on demand
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-27 15:27:38 -04:00