Commit Graph

105525 Commits

Author SHA1 Message Date
Alex Smith 3bd239f71d anv: Fix sanitization of stencil state when the depth test is disabled
When depth testing is disabled, we shouldn't pay attention to the
specified depthCompareOp, and just treat it as always passing. Before,
if the depth test is disabled, but depthCompareOp is VK_COMPARE_OP_NEVER
(e.g. from the app having zero-initialized the structure), then
sanitize_stencil_face() would have incorrectly changed passOp to
VK_STENCIL_OP_KEEP.

v2: Roll the depthTestEnable check into the ds_aspect check below since
    they now both do the same thing.

Fixes: 028e1137e6 "anv/pipeline: Be smarter about depth/stencil state"
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-26 10:25:40 +01:00
Samuel Pitoiset 79bbdf8e45 radv: implement image to image operations for R32G32B32
This should address the remaining failures in Batman Arkhman City.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107765
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-26 10:50:08 +02:00
Samuel Pitoiset 6198245775 radv: fix a comment in radv_meta_buffer_to_image_cs_r32g32b32()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-26 10:50:05 +02:00
Samuel Pitoiset 02ccef7874 radv: add get_image_stride_for_r32g32b32() helper
For the special R32G32B32 paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-26 10:50:03 +02:00
Samuel Pitoiset 468c33e2f7 radv: add create_bview_for_r32g32b32() helper
For the special R32G32B32 paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-26 10:50:00 +02:00
Samuel Pitoiset e60e3e1b3f radv: add create_buffer_from_image() helper
For the special R32G32B32 paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-26 10:49:58 +02:00
Sagar Ghuge 416abe809a intel/compiler: Print message descriptor as immediate source
While disassembling send(c) instruction print message descriptor as
immediate source operand along with message descriptor. This allows
assembler to read immediate source operand and set bits accordingly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-10-26 06:42:14 +02:00
Sagar Ghuge d15fa24860 intel/compiler: Print hex representation along with floating point value
While encoding the immediate floating point values in instruction we use
values upto precision 9, but while disassembling, we print precision to
6 places, which round up the value and gives wrong interpretation for
encoded immediate constant.

To avoid misinterpretation of encoded immediate values in instruction
and disassembled output, print hex representation along with floating
point value which can be used by assembler in future.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-10-26 06:41:08 +02:00
David McFarland 07a00a8729 util: Change remaining uint32 cache ids to sha1
After discussion with Timothy Arceri. disk_cache_get_function_identifier
was using only the first byte of the sha1 build-id.  Replace
disk_cache_get_function_identifier with implementation from
radv_get_build_id.  Instead of writing a uint32_t it now writes to a
mesa_sha1.  All drivers using disk_cache_get_function_identifier are
updated accordingly.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Fixes: 83ea8dd99b ("util: add disk_cache_get_function_identifier()")
2018-10-26 14:49:22 +11:00
Hyunjun Ko 3d198926a4 freedreno: use fd_bc_alloc_batch instead of fd_batch_create.
Following the commit 2385d7b066 and 8e798e28f7, for resource dependancy
tracking.

Fixes: dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
with FD_MESA_DEBUG=inorder

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-25 18:46:19 -04:00
Hyunjun Ko 703271c22a freedreno/ir3: take reg->num out of union in ir3_register
To avoid wrong result when identifying the type of register.
Ie. If the reg is an array, it might be identified as address or
predicate register.

Fixes: dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-25 18:45:45 -04:00
Rob Clark 3c402d0dc2 freedreno/a6xx: disable unused groups
Don't leave vsconst/fsconst group enabled if we switch to shader with no
uniforms.

Fixes: abcdf5627a freedreno/a6xx: move const emit to state group
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-25 18:38:53 -04:00
Rob Clark d53074d3f1 freedreno: add useful assert
Would have been useful to catch the problem fixed in
8e798e28f7

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-25 18:38:53 -04:00
Alok Hota edf38019a0 swr/rast: ignore CreateElementUnorderedAtomicMemCpy
This function's API changed between LLVM 5 and 6. Compile errors occur
when building with LLVM 6+ if LLVM 5 was used for a dist tarball

CC: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107865
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-25 11:05:59 -05:00
Alok Hota 8c872ac2e3 swr/rast: fix intrinsic/function for LLVM 7 compatibility
Converted from x86 VFMADDPS intrinsic to generic LLVM intrinsic, and
removed createInstructionSimplifierPass, which were both removed in LLVM
7.0.0

These changes combine patches we received from the community and our own
internal patches

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tested-by: Chuck Atkins <chuck.atkins@kitware.com>
2018-10-25 10:32:27 -05:00
Rhys Perry 26ed0f0234 nvc0: increase NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD to 1024 on Kepler+
Gives a +3.89% to +5.27% FPS improvement with Hitman and +2.73% to +2.82%
FPS improvement with Dirt Rally on my GTX 1060.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-10-25 15:25:10 +01:00
Bas Nieuwenhuizen d41c3cc013 radv: Emit enqueued pipeline barriers on event write.
Since the CPU can read them we need to execute any GPU->CPU
flushes before the event is written.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-25 16:17:54 +02:00
Bas Nieuwenhuizen 9d40ec2cf6 radv: Add support for VK_KHR_driver_properties.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-25 16:14:43 +02:00
Eric Engestrom e27902a261 util: use C99 declaration in the for-loop set_foreach() macro
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-25 12:43:18 +01:00
Eric Engestrom bb84fa146f util: use C99 declaration in the for-loop hash_table_foreach() macro
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-25 12:43:18 +01:00
Dylan Baker 3d261cf77b gen: Add AMD_gpu_shader_int64.xml to tarball
CC: Ian Romanick <ian.d.romanick@intel.com>
CC: Marek Olšák <marek.olsak@amd.com>
Fixes: b3c17330e6
       ("mesa: expose AMD_gpu_shader_int64")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2018-10-24 11:29:30 -07:00
Dylan Baker 6d5fa65c74 gen: Add EXT_vertex_attrib_64bit.xml to dependency lists
Which is also required to put it in the tarball, a requirement for
building with meson from the tarball.

CC: Ian Romanick <ian.d.romanick@intel.com>
CC: Marek Olšák <marek.olsak@amd.com>
Fixes: 263c962cfd
       ("mesa: expose EXT_vertex_attrib_64bit")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2018-10-24 11:29:29 -07:00
Eric Engestrom edc06dd533 anv: move variable to proper scope and mark as MAYBE_UNUSED
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-24 18:16:20 +01:00
Eric Engestrom ed5d65a6a1 anv: use snprintf() instead of memset()+strcpy()
snprintf() guarantees that it will not write more chars than allowed,
and that the string will be null-terminated, without the need to fill
the whole thing with zeroes to begin with.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-24 18:15:56 +01:00
Eric Engestrom 33d757096d anv: drop unused includes
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-10-24 18:15:05 +01:00
Dylan Baker c4de8ba036 autotools: include intel_tiled_memcopy.c
There are two problems with the fixed patch. First, it fails to create a
dependency on the sourced .c file, so changes to intel_tiled_memcpy.c
won't trigger a rebuild. It also doesn't get included in the dist
tarball.

Fixes: 11b1afdc92
       ("i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2018-10-24 09:22:15 -07:00
Dylan Baker 43b0d5fa04 meson: fix formatting and add extra_files to i965
extra_files is just a nice way to to tell certain IDEs (and those
reading the file) that this file is also a dependency. Meson will use
the .d file generated by the compiler to figure out what the target
actually depends on.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2018-10-24 09:22:13 -07:00
Eduardo Lima Mitev b0c427043b ir3_compiler/nir: fix imageSize() for buffer-backed images
GL_EXT_texture_buffer introduced texture buffers, which can be used
in shaders through a new type imageBuffer.

Because how image access is implemented in freedreno, calling
imageSize on an imageBuffer returns the size in bytes instead of texels,
which is incorrect.

This patch adds a division of imageSize result by the bytes-per-pixel
of the image format, when image is buffer-backed.

Fixes all tests under
dEQP-GLES31.functional.image_load_store.buffer.image_size.*

v2: Pre-compute and submit the log2 of the image format's bpp as shader
    constant instead of emitting the LOG2 instruction in code. (Rob Clark)

v3: Use ffs (find-first-bit) helper for computing log2 (Ilia Mirkin)

Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-10-24 18:18:35 +02:00
Jose Fonseca d9a04196d9 nir: Fix array initializer.
Empty initializer is not standard C.  This fixes MSVC build.

Trivial.
2018-10-24 11:37:09 +01:00
Liviu Prodea d99fda17c8 scons: Put to rest zombie texture_float build option.
I found a remnant of texture_float build option that wasn't removed in
commit 66673bef94

This patch removes it.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2018-10-24 11:10:17 +01:00
Alex Smith 6c56c1fbd4 anv: Allow presenting via a different GPU
anv_GetPhysicalDeviceSurfaceSupportKHR will already return success for
this, but anv_GetPhysicalDevice{Xcb,Xlib}PresentationSupportKHR do not.
Apps which check for presentation support via the latter (all Feral
Vulkan games at least) will therefore fail.

This allows me to render on an Intel GPU and present to a display
connected to an AMD card (tested HD 530 + Vega 64).

v2: Rebase on current master.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-24 09:40:02 +01:00
Juan A. Suarez Romero 3112da346b nir: fix nir_copy_propagation test
Use nir_src_comp_as_uint() to read the proper second component, as
nir_src_as_uint() returns the first one.

v2: Use nir_src_comp_as_uint() [Jason]

Fixes: 16870de8a0 ("nir: Use nir_src_is_const and nir_src_as_* in core
                     code")
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108532
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-24 09:13:24 +02:00
Timothy Arceri 0ff1ccca25 radv: call nir_link_xfb_varyings()
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-24 08:21:29 +11:00
Timothy Arceri c769ed10de radv: move nir_lower_io_to_scalar_early() to radv_link_shaders()
nir_lower_io_to_scalar_early() is really part of the link time
optimisations. Moving it here allows the code to be simplified
and also keeps the code easy to follow in the next patch.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-10-24 08:21:29 +11:00
Samuel Pitoiset 7c694cbfa4 nir: add linking helper nir_link_xfb_varyings()
The linking opts shouldn't try removing or compacting XFB varyings
in the consumer. To avoid this we copy the always_active_io flag
from the producer.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-10-24 08:21:29 +11:00
Sagar Ghuge 0a7664fe8c intel/compiler: Change src1 reg type to unsigned doubleword
To have uniform behavior while disassembling send(c) instruction use
register type of unsigned doubleword for src1 when message descriptor is
immediate value. Bspec does not specifiy anything for src1 immediate
default type.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
2018-10-23 12:44:24 -07:00
Eduardo Lima Mitev 22ddd4988e mesa/glformats: Remove redundant helper _mesa_base_format_component_count
There exists _mesa_components_in_format() which already includes
all cases handled in _mesa_base_format_component_count().

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-10-23 21:29:15 +02:00
Jason Ekstrand ecb7775e1c nir/algebraic: Fix a typo in the bit size validation code
The conon_bit_class and canon_var_class variables got switched.

Fixes: 932c650e0b "nir/algebraic: Loosen a restriction on variables"
Reported-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-23 12:22:29 -05:00
Leo Liu b75fb8ee36 amd/common: check DRM version 3.27 for JPEG decode
JPEG was added after DRM version 3.26

Signed-off-by: Leo Liu <leo.liu@amd.com>
Fixes: 4558758c51749(amd/common: add vcn jpeg ip info query)
Cc: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-23 13:12:05 -04:00
Juan A. Suarez Romero a8c2a6b0ac docs: update calendar
I'll take care of 18.2 releases series on Andres behalf.

CC: Andres Gomez <agomez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-23 18:40:09 +02:00
Lionel Landwerlin a8594887bc intel/decoders: fix end of batch limit
Pointer arithmetic...

v2: s/4/sizeof(uint32_t)/ (Eric)

v3: Give bytes to print_batch() in error_decode (Lionel)
    Make clear what values we're dealing with in error_decode (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v2)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-10-23 14:49:33 +01:00
Boyuan Zhang 55e7de7b19 radeonsi: enable vcn jpeg decode for raven
Enable vcn jpeg decode for raven.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 97c473bb29 winsys/amdgpu: add vcn jpeg cs support
Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 4558758c51 amd/common: add vcn jpeg ip info query
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 6d2d910653 radeon/vcn: implement jpeg target buffer cmd
Implement jpeg target buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 0ee5630cfc radeon/vcn: implement jpeg bitstream buffer cmd
Implement jpeg bitstream buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 9b478b0c7a radeon/uvd: remove get mjpeg slice header
Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 4fc2368e3b st/va: get mjpeg slice header
Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang c7a5ef26ad radeon/vcn: add jpeg decode implementation
Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00
Boyuan Zhang 40fceb55f3 radeon/vcn: separate send cmd call from end frame
Use function pointer for sending cmd in end_frame call. By doing this, we can
assign different cmd sending logics for Jpeg decode later.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2018-10-23 08:50:02 -04:00