Commit Graph

74859 Commits

Author SHA1 Message Date
Matt Turner ecac1aab53 i965: Push down inclusion of brw_program.h.
We were including it in headers, which then caused it to be included in
tons of places it wasn't needed.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:33 -08:00
Matt Turner 64cc7572c1 i965: Mark functions called from C as extern "C".
These functions' prototypes are marked with extern "C", which apparently
overrides a lack of extern "C" at the definition site if the prototype
has been seen first.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:33 -08:00
Matt Turner fb86f0e75a i965: Push down inclusion of vbo/vbo.h.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:33 -08:00
Matt Turner 6fe9ea78fa i965: Remove duplicate #includes.
Added in commits 36fd65381 and 337dad8ce even though the existing
include was in view.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:33 -08:00
Matt Turner c06f3d5d54 i965: Remove unneeded forward declarations.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:32 -08:00
Matt Turner e768c498bf i965: Mark count_trailing_one_bits() static.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:32 -08:00
Matt Turner 836aaa4394 i965: Remove useless gen6_blorp.h/gen7_blorp.h headers.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-24 10:05:32 -08:00
Matt Turner d956335a0b util: Include assert.h in macros.h. 2015-11-24 10:05:32 -08:00
Matt Turner fafbf994cf util: Include <stdbool.h> in debug.h. 2015-11-24 10:05:32 -08:00
Matt Turner 2d8c529903 i965: Prevent implicit upcasts to brw_reg.
Now that backend_reg inherits from brw_reg, we have to be careful to
avoid the object slicing problem.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-11-24 09:58:33 -08:00
Matt Turner 799f924073 i965: Use scope operator to ensure brw_reg is interpreted as a type.
In the next patch, I make backend_reg's inheritance from brw_reg
private, which confuses clang when it sees the type "struct brw_reg" in
the derived class constructors, thinking it is referring to the
privately inherited brw_reg:

brw_fs.cpp:366:23: error: 'brw_reg' is a private member of 'brw_reg'
fs_reg::fs_reg(struct brw_reg reg) :
                      ^
brw_shader.h:39:22: note: constrained by private inheritance here
struct backend_reg : private brw_reg
                     ^~~~~~~~~~~~~~~
brw_reg.h:232:8: note: member is declared here
struct brw_reg {
       ^

Avoid this by marking brw_reg with the scope resolution operator.
2015-11-24 09:58:33 -08:00
Matt Turner f093c842e6 i965: Use implicit backend_reg copy-constructor.
In order to do this, we have to change the signature of the
backend_reg(brw_reg) constructor to take a reference to a brw_reg in
order to avoid unresolvable ambiguity about which constructor is
actually being called in the other modifications in this patch.

As far as I understand it, the rule in C++ is that if multiple
constructors are available for parent classes, the one closest to you in
the class heirarchy is closen, but if one of them didn't take a
reference, that screws things up.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-11-24 09:58:33 -08:00
Matt Turner 309a44d63c i965: Add and use backend_reg::equals().
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-11-24 09:58:33 -08:00
Roland Scheidegger 6c6a439e98 softpipe/llvmpipe: don't advertize support for ASTC
3333977556 added support for ASTC textures to
gallium. They don't have any helpers hooked up for software decoding, however,
so cannot support them in drivers relying on util code for decoding.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-24 18:26:11 +01:00
Roland Scheidegger 97eed8dcb9 llvmpipe: don't test for unsupported formats in lp_test_format
Removing the fake format helpers (1c7d0a6aa4)
caused this to fail. These formats were never supported, but previously
they would have asserted in the generated jit functions (which, due to lack
of test cases for these formats, were never called) whereas we now assert when
trying to build the jit function. So, skip them completely.

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=93092

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-24 18:26:11 +01:00
Ian Romanick 9b41489cb5 docs: add missed i965 feature to relnotes
Trivial.  GL_ARB_fragment_layer_viewport support was added in 8c902a58
by Ken.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-11-24 09:03:39 -08:00
Rob Clark d278e31459 util: move brw_env_var_as_boolean() to util
Kind of a handy function.  And I'll want it available outside of i965
for common nir-pass helpers.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nhaehnle@gmail.com>
2015-11-24 10:02:55 -05:00
Christian König d3e2c48dfa st/va: fix indentation
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:48 +01:00
Christian König 64761a841d st/va: move MPEG4 functions into separate file
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:45 +01:00
Christian König 9fe7924328 st/va: move VC-1 functions into separate file
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:41 +01:00
Christian König da173344a6 st/va: move H264 functions into separate file
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:38 +01:00
Christian König c9cb22392b st/va: move MPEG12 functions into separate file
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:35 +01:00
Christian König ec6ef1cbfe st/va: move post processing function into own file
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:31 +01:00
Christian König 3d6386fdc5 st/va: fix post process dirty area handling
The dirty area in this call isn't related to the screen at all.

v2: set clear dirty area to false as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-11-24 15:31:11 +01:00
Timothy Arceri 2571a768d6 glsl: implement recent spec update to SSO validation
Enables 200+ dEQP SSO tests to proceed past validation,
and fixes a ES31-CTS.sepshaderobjs.PipelineApi subtest.

V2: split out change that reverts a previous patch into its own commit,
move variable declaration to top of function, and fix some formatting
all suggested by Ian.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-11-24 20:59:48 +11:00
Timothy Arceri 3c4aa7aff2 Revert "mesa: return initial value for VALIDATE_STATUS if pipe not bound"
This reverts commit ba02f7a3b6.

The commit checked whether the pipeline was currently bound instead
of checking whether it had ever been bound.  The previous setting
of Validated during object creation makes this unnecessary.  The
real problem was that Validated was not properly set to false
elsewhere in the code.  This is fixed by a later patch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-11-24 20:59:44 +11:00
Michel Dänzer d094631936 radeon/llvm: Use llvm.AMDIL.exp intrinsic again for now
llvm.exp2.f32 doesn't work in some cases yet.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-24 18:07:48 +09:00
Boyuan Zhang f55f134a03 radeon/uvd: uv pitch separation for stoney
v2: set the behaviour default for future ASICs.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-11-23 17:34:43 -05:00
Dave Airlie 237bcdbab5 texgetimage: consolidate 1D array handling code.
This should fix the getteximage-depth test that currently asserts.

I was hitting problem with virgl as well in this area.

This moves the 1D array handling code to a single place.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-24 06:43:21 +10:00
Jason Ekstrand d9b8fde963 i965: Use NIR for lowering texture swizzle
Now that nir_lower_tex can do texture swizzle lowering, we can use that
instead of repeating more-or-less the same code in both backends.  This
both allows us to share code and means that things like the tg4
work-arounds are somewhat simpler because they don't have to take the
swizzle into account.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:07:32 -08:00
Jason Ekstrand 8537b4ab76 nir/lower_tex: Add support for lowering texture swizzle
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand 6921b17107 nir: Add a tex_instr_is_query helper
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand 7e83fd85aa nir: Add a ssa_def_rewrite_uses_after helper
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand 384396a69b nir: Use instr/if_rewrite in nir_ssa_def_rewrite_uses
nir_ssa_def_rewrite_uses is one of the older helpers in NIR and predated
both of those.  Now it can be substantially simplified.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand 03c9ad900e nir/validate: Validated dests after sources
Previously, if someone accidentally made an instruction that refers to its
own SSA destination, the validator wouldn't catch it.  The reason for this
is that it validated the destination too early and, by the time it got to
the source, the destination SSA value was already added to the set of seen
SSA values so it would assume that it came from some previous instruction.
By moving destination validation to be after source validation, the SSA
value is not in the list of seen values and the validator will catch
self-referential instructions.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand 6c8ba59cff i965: Use nir_lower_tex for texture coordinate lowering
Previously, we had a rescale_texcoords helper in the FS backend for
handling rescaling of texture coordinates.  Now that we can do variants in
NIR, we can use nir_lower_tex to do the rescaling for us.  This allows us
to delete the i965-specific code and gives us proper TEXTURE_RECTANGLE and
GL_CLAMP handling in vertex and geometry shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-23 11:04:49 -08:00
Jason Ekstrand d065a93a3f i965/fs: Stomp the texture return type to UINT32 for resinfo messages
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-23 11:02:15 -08:00
Jason Ekstrand 042fa75e48 nir/lower_tex: Set the dest_type for txs instructions
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand 1417f6a216 nir/lower_tex: Report progress
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand ce767bbdff i965: Move postprocess_nir to codegen time
This allows us to insert NIR passes between initial NIR compilation and
optimization (link time) and actual backend code-gen.  In particular, it
will allow us to do shader variants in NIR and share some of that shader
variant code between backends.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand 9cf108193b i965/nir: Split shader optimization and lowering into three stages
At the moment, brw_create_nir just calls the three stages in sequence so
there's not much difference.  Soon, however, we will want to start doing
variants in NIR at which point the postprocessing step will have to move
from shader create time to codegen time.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand 9d703de85a i965: Use ull immediates in brw_inst_bits
This fixes a regression introduced in b1a83b5d1 that caused basically all
shaders to fail to compile on 32-bit platforms.

Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-11-23 10:55:38 -08:00
Ilia Mirkin e4c1221d36 docs: add missed freedreno features to relnotes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-11-23 12:32:54 -05:00
Ilia Mirkin 33dc9aac07 docs: update relnotes with new freedreno/a4xx support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 12:32:54 -05:00
Jose Fonseca c9651f0264 svga: Add ASTC formats to format table.
Fixes build.  Otherwise untested.

Trivial.
2015-11-23 16:45:28 +00:00
Ilia Mirkin 754b26e76d freedreno/ir3: add support for a few gs5 ops
Tested on a4xx. This is part of the builtins added by ARB_gpu_shader5
and GLSL ES 3.10.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:16 -05:00
Ilia Mirkin cca8dd4e93 ttn: fix UMSB conversion
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:16 -05:00
Ilia Mirkin 190acb34ca freedreno/a4xx: add ARB_texture_query_lod support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin f0e670bdd7 ttn: add LODQ support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin 9761d5146f freedreno/a4xx: re-emit program on dirty framebuffer
The program emit depends on certain fb details. Make sure those get
updated when the fb changes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00