Commit Graph

109778 Commits

Author SHA1 Message Date
Guido Günther 10b90570d1 docs: Fix 19.0.x version numbers
The list has 19.0.2 twice.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-04-02 09:12:47 -07:00
Marek Olšák 40b9eec8bd docs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0 2019-04-02 10:47:37 -04:00
Benjamin Tissoires 7f8a9a1fbb CI: use wayland ci-templates repo to create the base image
There shouldn't be a difference for users, but this way we do manage
all of our containers from freedesktop.org

note: compared to the provious Dockerfile, we need to manually
      add gcc, g++ and python*-wheel

Signed-off-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-04-02 13:41:05 +00:00
Marek Olšák 7be26976b8 radeonsi: don't use PFP_SYNC_ME with compute-only contexts
Compute rings don't have PFP.

Fixes: a1378639ab "radeonsi: always use compute rings for clover on CI and newer (v2)"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-04-02 08:46:49 -04:00
Gert Wollny 1e5381f934 virgl: define MAX_VERTEX_STREAMS based on availability of TF3
Since with gles hosts we lie about the GLSL feature level it is better
to set the number of streams based on actual hosts capabilities.

v2: Make use of feature check level to avoid regressions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By:  Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-02 11:28:09 +00:00
Gert Wollny 33d9b9436c softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD
This enables the following piglits with PASS:
  nv_shader_atomic_float/execution/
    shared-atomicadd-float
    shared-atomicexchange-float
    ssbo-atomicadd-float
    ssbo-atomicexchange-float

v2: Minimize the patch by using type punning (Eric Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-04-02 09:58:16 +00:00
Erik Faye-Lund 4f153fcd5c virgl: stricter usage of compressed 3d textures
Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of
OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc,
EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture,
S3_s3tc or EXT_texture_compression_s3tc specifications.

So let's not allow any of those compressed 3d-textures at all. It's not
going to work once it hits the OpenGL driver in virglrenderer.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-02 07:48:46 +00:00
Erik Faye-Lund f53001324f virgl: do not allow compressed formats for buffers
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-02 07:48:45 +00:00
Eric Anholt edc7deec42 dri3: Return the current swap interval from glXGetSwapIntervalMESA().
We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader.  This fixes
glxgears's warning about being vblank synchronized by default.

Fixes: 9777c4234b ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-04-01 16:06:38 -07:00
Anuj Phogat 82f6a746e8 intel: Add support for Comet Lake
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-04-01 14:07:40 -07:00
Chris Wilson 80e1ca9d28 iris: Adapt to variable ppGTT size
Not all hardware is made equal and some does not have the full
complement of 48b of address space. Ask what the actual size of virtual
address space allocated for contexts, and bail if that is not enough to
satisfy our static partitioning needs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-01 10:01:02 -07:00
Samuel Pitoiset c25f63872b radv: partially enable VK_KHR_shader_float16_int8
Only 8-bit integers for now, float16 requires a bit more work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:59 +02:00
Samuel Pitoiset d099bc5829 ac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:57 +02:00
Samuel Pitoiset 2cecf6c5cc ac: add 8-bit support to ac_build_umsb()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:55 +02:00
Samuel Pitoiset a45d9e3e8d ac: add 8-bit support to ac_find_lsb()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:53 +02:00
Samuel Pitoiset 89cf8ca0ae ac: add 8-bit support to ac_build_bit_count()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:52 +02:00
Samuel Pitoiset 869af0464a ac/nir: add support for nir_op_b2i8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:49 +02:00
Marek Olšák b9d627e076 radeonsi: implement ARB/KHR_parallel_shader_compile callbacks 2019-04-01 12:37:52 -04:00
Marek Olšák 050fae3983 util/queue: add util_queue_adjust_num_threads
for ARB_parallel_shader_compile

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-04-01 12:37:52 -04:00
Marek Olšák b7317b6ce0 util/queue: hold a lock when reading num_threads in util_queue_finish
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-04-01 12:37:52 -04:00
Marek Olšák bb111559f2 util/queue: add ability to kill a subset of threads
for ARB_parallel_shader_compile
2019-04-01 12:37:52 -04:00
Marek Olšák d99cdc9d59 util/queue: move thread creation into a separate function
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-04-01 12:37:52 -04:00
Marek Olšák e871cbd625 gallium: implement ARB/KHR_parallel_shader_compile 2019-04-01 12:37:52 -04:00
Marek Olšák c5c38e831e mesa: implement ARB/KHR_parallel_shader_compile
Tested by piglit.
2019-04-01 12:37:52 -04:00
Marek Olšák 3ad2a9b3fa radeonsi: fix assertion failure by using the correct type
src/gallium/drivers/radeonsi/si_state_viewport.c:196: si_emit_guardband:
Assertion `vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode]
&& vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]' failed.

The comparison was unsigned, so negative maxx or maxy would fail.

Fixes: 3c540e0a74 "radeonsi: Fix guardband computation for large render targets"
2019-04-01 12:21:20 -04:00
Leo Liu d4e0fbc92f radeon/vcn/vp9: search the render target from the whole list
The number of render targets could be more than max of references,
so we search the full list of the render pictures for the current
render target index

https://bugs.freedesktop.org/show_bug.cgi?id=109648

Signed-off-by: Leo Liu <leo.liu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: James Zhu<James.Zhu@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>
2019-04-01 08:59:38 -04:00
Rhys Perry 0af95f0ffc radv: lower 16-bit flrp
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-04-01 09:58:48 +02:00
Samuel Pitoiset 4d5fce29c3 ac: fix ac_build_umsb() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 09:51:56 +02:00
Samuel Pitoiset 7a088d1ac8 ac: fix ac_find_lsb() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 09:51:54 +02:00
Samuel Pitoiset b16dffff23 ac: fix ac_build_bitfield_reverse() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 09:51:52 +02:00
Samuel Pitoiset 9d13b9e53e ac: fix ac_build_bit_count() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 09:51:49 +02:00
Samuel Pitoiset e39a6b940f ac/nir: fix nir_op_b2i16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 09:51:47 +02:00
Eric Engestrom aa7afe324c meson: strip rpath from megadrivers
More specifically, use the library file that has been post-processed by Meson
when creating the hardlinks.

Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108766
Fixes: 3218056e0e "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-04-01 07:04:13 +00:00
Tapani Pälli 06f40f5765 spirv: fix a compiler warning
Fixes implicit conversion from enumeration type 'SpvOp' warning.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-04-01 07:43:10 +03:00
Lionel Landwerlin f0b472b301 i965: perf: update render basic configs for big core gen9/gen10
This updates allows an MI_LRI to trigger a OA report write in the
global OA buffer. This isn't really useful for us, we just keep close
to the internal public configs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-01 00:59:31 +03:00
Lionel Landwerlin 052ace0c81 i965: perf: add ring busyness metric for cfl gt2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-01 00:59:26 +03:00
Lionel Landwerlin 7e54857b4a i965: perf: enable Icelake metrics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:36:37 +01:00
Lionel Landwerlin 897efc2059 i965: perf: add Icelake metrics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:36:37 +01:00
Lionel Landwerlin b910e40956 i965: perf: sklgt2: drop programming of an unused NOA register
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Lionel Landwerlin 29ce64a77a i965: perf: hsw: drop register programming not needed on HSW
This register is flagged as IVB only in the documentation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Lionel Landwerlin 46250d7dac i965: perf: chv: fixup counters names
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Lionel Landwerlin 046041b2a0 i965: perf: add PMA stall metrics
These are new metrics for Gen8/9 to measure the effect of the PMA
stall workaround fix.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Lionel Landwerlin dc9e598f3c i965: perf: sklgt2: update memory write config
This rework the programming between older pre-production steppings &
new ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Lionel Landwerlin 0d618bb635 i965: perf: sklgt2: update compute metrics config
This unifies some of the programming between pre-production stepping
and production ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Lionel Landwerlin 4edaa6f003 i965: perf: sklgt2: update a priority for register programming
This makes no difference in term of programming, it's just a cleanup.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-31 10:35:16 +01:00
Alyssa Rosenzweig e4e6a3deaf panfrost: Implement FIXED formats
Fixes crash in dEQP-GLES2.functional.draw.random.9

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-31 04:42:37 +00:00
Alyssa Rosenzweig ed160a1160 panfrost: Fix index calculation types and asserts
Fixes crash in
dEQP-GLES2.functional.draw.draw_elements.points.single_attribute.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-31 04:42:22 +00:00
Alyssa Rosenzweig 0e4c321c15 panfrost: Clean index state between indexed draws
Fixes subsequent tests in
dEQP-GLES2.functional.draw.draw_elements.indices.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-31 04:41:54 +00:00
Alyssa Rosenzweig 4fcd3189ae panfrost/decode: Print negative_start
This property slipped through..

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-31 04:41:06 +00:00
Alyssa Rosenzweig 9237204400 panfrost: Implement missing texture formats
- Implements RGB565/RGBA5551 formats
 - Don't advertise support for flipped RGBA5551 and ETC

Fixes remaining tests in dEQP-GLES2.functional.texture.format.* which is
now at 36/36.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-31 02:36:38 +00:00