Commit Graph

123396 Commits

Author SHA1 Message Date
D Scott Phillips 65b05ebdda anv,iris: Fix input vertex max for tcs on gen12
gen12 does away with the single patch dispatch mode for tcs, and
increases some limits so that 8_patch mode can always work. Make the
necessary changes so we don't try to fall back to single patch mode.

Fixes KHR-GL46.tessellation_shader.single.max_patch_vertices and others

Fixes: 44754279ac ("intel/fs/gen12: Use TCS 8_PATCH mode.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4843>
2020-05-01 16:49:11 +00:00
Eric Anholt 8f01fa1fb3 freedreno/ir3: Set the FS .msaa flag to true during precompiles.
If you're going out of your way to do per-sample interpolation, you are
almost surely going to be doing so to an MSAA framebuffer.  Should reduce
recompiles with MSAA enabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt 812c55b079 freedreno: Immediately compile a default variant of shaders.
Now that we normalize our keys fairly well, build a variant at shader
state creation time so that hopefully you don't have to call the compiler
at draw time (as is now the case with glmark2 ES and most of the humus GL
demos).

Fixes: #2782
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt 29f58cfbd0 freedreno/ir3: Set up outputs for multi-slot varyings.
Necessary to avoid compiler assertion failures in:

dEQP-GLES31.functional.program_interface_query.program_output.type.interface_blocks.out.named_block_explicit_location.struct.mat3x2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt 88dcfaf0ee freedreno/ir3: Stop initializing regid of so->outputs during setup.
It's unused and overwritten by ir3_compile_shader_nir().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt 8c1c218909 freedreno/ir3: Improve shader key normalization.
We can remove a bunch of conditional code at key comparison time by
computing a bitmask of used key bits at ir3_shader creation time.  This
also gives us a nice place to put additional key simplification to reduce
how many variants we create (like skipping rastflat if we don't read
colors in the FS, or skipping vclamp_color if we don't write colors).

It does mean walking the whole key to AND it, but the key is just 28 bytes
so far so that seems pretty fine.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt 6f1e3235f2 freedreno: Emit debug messages when doing draw-time recompiles of shaders.
Right now that's "always" unless you have shaderdb set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt a361567c46 freedreno/ir3: Remove unused half precision shader key flag.
The code using it was removed in 4af86bd0b9 ("freedreno/ir3: remove
half-precision output")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt 05be0659fe freedreno: Fix assertion failures on GS/tess shaders with shader-db enabled.
We weren't filling in the tess mode of the key, or setting has_gs on GS
shaders, resulting in assertion failures when NIR intrinsics didn't get
lowered.

We have to make a guess at prim mode for TCS, but it should be better to
have some shader-db coverage than none, and it will avoid these failures
happening when we start precompiling shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt f91e49ee29 freedreno/ir3: Skip tess epilogue if the program is missing stores.
Some of the negative API tests make shaders for tess stages that don't do
all the stores they need to.  Once we start precompiling (or doing
shader-db of tess), we need to at least not segfault when generating them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt fd8f3b62a4 freedreno: Stop doing binning shaders other than the VS in shader-db.
ir3_cache.c only ever asks for binning variants for VS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Eric Anholt b420d04e1f freedreno/ir3: Fix register allocation assertion failures.
We were failing to tell the allocator about the restriction that scalar
texture instructions (allocated as scalar regs) couldn't be allocated such
that the start of the full unwritemasked vector started before r0.  There
was a patch in select_reg_callback on a6xx that tried to work around that,
but you could still end up backed into a corner you shouldn't be because
we didn't tell the RA what it needed.

Fixes compiler assertion failures on a300-a400's blit_z shader, used for
Z32F gmem blits.

Looks like as a result we get tighter register allocation but more nops:

instructions in affected programs: 757945 -> 760356 (0.32%)
nops in affected programs: 317983 -> 320468 (0.78%)
non-nops in affected programs: 27525 -> 27451 (-0.27%)
mov in affected programs: 3098 -> 3023 (-2.42%)
dwords in affected programs: 109664 -> 110656 (0.90%)
last-baryf in affected programs: 112701 -> 112847 (0.13%)
full in affected programs: 4326 -> 4011 (-7.28%)
sstall in affected programs: 120550 -> 120836 (0.24%)
(ss) in affected programs: 13939 -> 13918 (-0.15%)
(sy) in affected programs: 3006 -> 2786 (-7.32%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:32 +00:00
Kristian H. Kristensen 73f34e0d46 freedreno/ir3: Drop hack to clean up split vars
When the GS lowering was working on store_output intrinsics, we had to
clean up the split vars to avoid getting confused.  Now that we shadow
the output vars instead, there's no confusion and we can drop this
hack.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
Kristian H. Kristensen dd8d257a30 freedreno/ir3: Lower GS builtins before lowering IO
We mostly got away with replacing a store_output with a store_var, but
for complex types like structs, that doesn't work. Once the IO has
been lowered from vars to intrinsic, we've lost the deref chains and
can't properly shadow the outputs.

This commits moves the GS lowering up so we do it before the output
variables get lowered to store_output.  This way the pass works much
like nir_lower_io_to_temporaries() and cleanly shadows the outputs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
Kristian H. Kristensen 79355fd901 freedreno/ir3: Add ir3_nir_lower_to_explicit_input() pass
This pass lowers per-vertex input intrinsics to load_shared_ir3. This
was open coded in the TCS and GS lowering passes before - this way we
can share it. Furthermore, we'll need to run the rest of the GS
lowering earlier (before lowering IO) so we need to split off this
part that operates on the IO intrinsics first.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
Kristian H. Kristensen b7bfccf085 freedreno/ir3: Rename ir3_nir_lower_to_explicit_io
We rename it to ir3_nir_lower_to_explicit_output, since it only
handles output and we'll add a lowering pass for input next.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
Kristian H. Kristensen a16ee14f37 freedreno/ir3: Pass stream output info to ir3_shader_from_nir
We need shader->stream_output filled out when we layout the push
constants in ir3_setup_const_state(). Otherwise
const_state->offsets.tfbo ends up as ~0, which doesn't work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
Eric Anholt 07f89126cd freedreno/ir3: Fix the a3xx TF outputs stores.
We were trying to deref the vector-collected outputs[] array before it's
been set up, but we want the per-component outputs anyway.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
Eric Anholt b0b8011e3e freedreno/ir3: Set up the block predecessors for a3xx TF
Fixes a segfault in ir3_legalize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
2020-05-01 16:26:31 +00:00
D Scott Phillips 7bd15135a6 intel/fs: Update location of Render Target Array Index for gen12
Render Target Array Index has moved from R0.0[26:16] to
R1.1[26:16] on gen12.

Fixes dEQP-VK.multiview.input_attachments.*

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4836>
2020-05-01 08:48:22 -07:00
Tomeu Vizoso 7eb2bc8f52 pan/decode: Properly print tripped zeroes
The "%" got lost.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes: 6148d1be4b ("panfrost: Fix size of bifrost sampler descriptor")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:46 +02:00
Tomeu Vizoso 3a81abf3b2 panfrost: Add Bifrost texture trampoline BO to batch
Fixes: d3eb23adb5 ("panfrost: Emit sampler descriptor on bifrost")
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:40 +02:00
Alyssa Rosenzweig c46731527a pan/bi: Lower for now sincos
Will be implemented later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:36 +02:00
Tomeu Vizoso 3baf251487 panfrost: mali_attr_meta.unknown1 is zero on Bifrost
For unknown1 reasons :)

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:32 +02:00
Tomeu Vizoso c4400b05be panfrost: GPUs newer than G-71 don't have swizzles...
for attributes and varyings.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:28 +02:00
Tomeu Vizoso c409428006 pan/decode: Trace to stderr with PANDECODE_DUMP_FILE=stderr
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:23 +02:00
Alyssa Rosenzweig d6588b87bf panfrost: Update Bifrost fields in mali_shader_meta
Not much is known currently about these fields and their values, but
this gets things going in the scenarios we have been testing with so
far.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:19 +02:00
Tomeu Vizoso 07b31f3437 pan/bi: Print shaders only if BIFROST_MESA_DEBUG=shaders
Similar to how it's done in the Midgard compiler.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:16 +02:00
Alyssa Rosenzweig 9c7d30fb4a pan/bi: Enable lower_mediump_outputs NIR pass
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:11 +02:00
Tomeu Vizoso 7104e28651 panfrost: Add a bit more info about some tiler fields
Has been observed that after the job chain has completed, those fields
become populated.

tiler_heap_next_start contains an address inside the tiler heap, a bit
before the value that the GPU writes to tiler_heap_free.

used_hierarchy_mask contains a hex value that corresponds to values
observed as hierarchy masks.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:07 +02:00
Tomeu Vizoso 4d581a4bc6 panfrost: Create additional BO for the checksum of imported BOs (Bifrost)
Similar to what the blob does. My reason for doing this was mainly so
traces weren't as different, which makes it more work to spot
relevant differences.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:52:03 +02:00
Tomeu Vizoso 28902ba87e panfrost: Split bit out of format.unk3
On Bifrost traces, we can observe that this bit is always enabled.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
2020-05-01 16:51:36 +02:00
Samuel Pitoiset 7f130e76ea ci: add lists of expected failures & skipped tests for RAVEN with ACO
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4848>
2020-05-01 16:07:47 +02:00
Andres Gomez 263ed2e777 scripts: remove unittest.mock dependency when not used
Found upon inspection.

Signed-off-by: Andres Gomez <agomez@igalia.com
Reviewed-and-Tested-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4840>
2020-05-01 15:01:51 +03:00
Samuel Pitoiset cc2c3b41b8 ci: fix reporting the number of unexpected/flakes
`wc -l $file` returns the number of lines and the filename.

Fixes: b8c66aeb93 ("ci: Clean up some excessive use of pipes in dEQP results processing.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4829>
2020-05-01 07:51:44 +00:00
Michel Dänzer 23daa49d4c gitlab-ci: Use YAML anchor for llvmpipe paths in virgl rules
Instead of duplicating them.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4808>
2020-05-01 07:19:05 +00:00
Rob Clark 60912f1ebd freedreno: we don't need aligned vbo's
This gets rid of the last reason that mesa/st would use `u_vbuf` on
a6xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4812>
2020-05-01 02:05:00 +00:00
Rob Clark 9a7c179473 freedreno/a6xx: add some more formats
u_vbuf was translating these for us.. which isn't really necessary.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4812>
2020-05-01 02:05:00 +00:00
Alyssa Rosenzweig 6f7d94580e pan/decode: Don't crash on missing payload
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig bde19c0e7b panfrost: Fix tiled texture "stride"s on Bifrost
They're not real strides like linear textures but the hw does use them
so we do have to get it right annoyingly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig bbecbedb4c panfrost: Fix norm coords on bifrost sampler
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig 401409eff3 panfrost: Fix sampler wrap/filter field orders
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig 6148d1be4b panfrost: Fix size of bifrost sampler descriptor
Should be 32-bytes, it looks like.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig 884f869992 panfrost: Fix texture field size
I have to imagine this was UB.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig d04be375cc pan/bit: Add round tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig 6bbedf8359 pan/bit: Interpret ROUND
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig f1f4f1b816 pan/bit: Add framework forinterpreting double vs float
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig 130a3fba1c pan/bi: Pack round opcodes (FMA, either 16 or 32)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig 5f35cdaa8d pan/bi: Pipe multiple textures through
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00
Alyssa Rosenzweig fc634dc3b2 pan/bi: Add texture indices to IR
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4844>
2020-05-01 00:27:23 +00:00