Commit Graph

8 Commits

Author SHA1 Message Date
Alyssa Rosenzweig 1d0008734c agx: Ensure we don't overallocate registers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751>
2021-07-07 03:31:43 +00:00
Alyssa Rosenzweig 85e18deb18 agx: Assign registers locally
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751>
2021-07-07 03:31:43 +00:00
Alyssa Rosenzweig 15b49a6795 agx: Count read registers as well
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751>
2021-07-07 03:31:43 +00:00
Alyssa Rosenzweig 2e1ba82060 agx: Count write registers, not components
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
2021-07-05 20:56:04 +00:00
Alyssa Rosenzweig ebd25e7ee7 agx: Pull out agx_write_components
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
2021-07-05 20:56:04 +00:00
Alyssa Rosenzweig 3d3e4928b2 agx: Add ld_vary_flat opcode
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
2021-07-05 20:56:03 +00:00
Alyssa Rosenzweig 1164c992cf agx: Add ld_tile opcode
Variant of st_tile.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10720>
2021-05-09 23:29:45 -04:00
Alyssa Rosenzweig c215895eae agx: Add a trivial register allocator
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-05-02 17:41:12 -04:00