Commit Graph

72098 Commits

Author SHA1 Message Date
Ilia Mirkin 581cbfdec1 freedreno/a3xx: fix up logic for handling block formats
This only appears in cubemaps which have have packed layers, so are very
sensitive to any layout disagreement between sw and hw.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 11:38:38 -04:00
Ilia Mirkin 12e1bf0b68 freedreno/a3xx: double the polygon offset value
A few other drivers do this, fixes the gl-1.4-polygon-offset piglit test

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 11:38:38 -04:00
Ilia Mirkin 1af0641db3 nvc0: implement the color buffer 0 is integer rule for alpha-to-one/cov
The hardware checks for multisampling being enabled, but does not have
the rule about cbuf0 being an integer format. Only enable
alpha-to-one/alpha-to-coverage if cbuf0 is not an integer format.

Fixes piglits
  ext_framebuffer_multisample-int-draw-buffers-alpha-to-one
  ext_framebuffer_multisample-int-draw-buffers-alpha-to-coverage

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 04:21:18 -04:00
Marta Lofstedt 19a5a91ea4 mesa: Raise INVALID_VALUE from glCreateShaderProgramv if count < 0
According to OpenGL version 4.5 and OpenGL ES 3.1 standards, section 7.3:
GL_INVALID_VALUE should be generated, if count is less than 0.

V2: Changed title, eased Open GL ES 3.1 restriction and added comments.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-08-17 10:29:07 +03:00
Marta Lofstedt dd9d2963d6 mesa: AtomicBufferBindings should be initialized to zero.
According to OpenGL specification version 4.5 table 23.46
and OpenGL ES specification version 3.1 table 20.31:
ATOMIC_COUNTER_BUFFER_START and ATOMIC_COUNTER_BUFFER_SIZE
should have the initial value of zero.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
2015-08-17 10:24:26 +03:00
Tapani Pälli a7e6f8cc9f mesa: fix target error checking in glGetTexLevelParameter
With non-dsa functions we need to do target error checking before
_mesa_get_current_tex_object which would just call _mesa_problem without
raising GL_INVALID_ENUM error. In other places of Mesa, target gets checked
before this call.

Fixes failures in:
   ES31-CTS.texture_storage_multisample.APIGLGetTexLevelParameterifv.*

v2: do the target check also for dsa functions (Timothy)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-08-17 10:02:52 +03:00
Ilia Mirkin 2f5ee9bf27 gk110/ir: fix sched calculator to consider all registers in the ISA
GK110/GK208 have 256 registers, not 64. Find out the number of registers
from the target to avoid unnecessary iteration for pre-GK110.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 02:46:16 -04:00
Timothy Arceri e32325fc85 mesa: rename texture function now that its static
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-08-17 15:38:21 +10:00
Tapani Pälli a0cea8f642 glsl: add missing MS sampler builtin types for GLSL ES 3.10
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-17 08:25:04 +03:00
Marta Lofstedt f67dde0b05 mesa: Implement glMemoryBarrierByRegion
The function glMemoryBarrierByRegion is part of OpenGL ES 3.1
and OpenGL 4.5 core and compatibility profiles.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-08-17 08:25:04 +03:00
Ilia Mirkin ae5cf4f3f7 nvc0: program smooth line width when multisampling is enabled
There are separate line widths for smooth and aliased lines. The smooth
one is selected when multisampling is enabled even if line smoothing
isn't explicitly turned on.

Fixes the ext_framebuffer_multisample-line-smooth piglits

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 01:01:02 -04:00
Ilia Mirkin 884b4df3b6 nvc0: bind a fake tess control program when there isn't one available
Apparently this is necessary in order for tess factors to work in a tess
eval program without a tess control program bound. Probably because it
uses the fake program's shader header to work out the number of patch
constants.

Fixes vs-tes-tessinner-tessouter-inputs

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 01:01:02 -04:00
Ilia Mirkin f13073b775 gm107/ir: avoid letting the lowering pass get out of sync
There's a lot of functionality duplicated in the gm107 lowering pass
from the nvc0 pass. As that one gets updated, the gm107 one falls
behind. Avoid this by sharing the code.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-17 01:01:02 -04:00
Ilia Mirkin 2514c78fba nv50,nvc0: take level into account when doing eng2d multi-layer blits
This fixes arb_get_texture_sub_image-get, and any situation where the 2d
engine was being used for multi-layer blits to a non-0 level.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
2015-08-17 01:01:02 -04:00
Ilia Mirkin bb9881fccf st/mesa: also move yoffset to zoffset for 1d array textures
Do the same as in st_TexSubImage. This fixes
arb_get_texture_sub_image-get on llvmpipe when it is set to prefer
blits, and nouveau when it uses the 3d engine for blits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-08-17 01:00:43 -04:00
Kenneth Graunke afccbd7256 nir: Add a glsl_uint_type() wrapper.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
2015-08-16 21:44:19 -07:00
Ilia Mirkin ca628085b6 freedreno/a3xx: add per-texture seamless cubemap control
The default is to enable seamless cubemap filtering, but there's a bit
to turn it off.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-16 03:01:53 -04:00
Ilia Mirkin b4ace13eea freedreno/a4xx: add cube map array support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-15 14:05:37 -04:00
Rob Clark 868b66fce7 freedreno/a4xx: fix srgb render targets
Also fixes mipmap level generation for srgb textures.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-15 12:09:06 -04:00
Rob Clark dd412c8fcb freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-15 12:08:34 -04:00
Vinson Lee ee113bbbc5 scons: Always define __STDC_LIMIT_MACROS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-08-15 01:44:33 -07:00
Ilia Mirkin d19a98e2e6 freedreno: expose OES exts for float linear filtering
a4xx can do both float and half-float, while a3xx can only do half-float

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-14 20:22:49 -04:00
Ilia Mirkin d3e23f1ff9 nvc0: disable tessellation on maxwell
The address calculations are all different (e.g. see GP), there appear
to be sync's in programs, and probably a bunch of other differences.
Just disable it for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-14 16:02:26 -04:00
Eric Anholt a6e75e3cd7 nir: Add support for CSE on textures.
NIR instruction count results on i965:
total instructions in shared programs: 1261954 -> 1261937 (-0.00%)
instructions in affected programs:     455 -> 438 (-3.74%)

One in yofrankie, two in tropics.  Apparently i965 had also optimized all
of these out anyway.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-14 11:39:18 -07:00
Eric Anholt fb2425a641 nir: Zero out texture instructions when creating them.
There are so many flags in textures, that the CSE pass would have a hard
time referencing the correct set when figuring out if two texture ops are
the same.  By zeroing, we can avoid that fragility.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-14 11:39:18 -07:00
Eric Anholt bf3c50fba2 vc4: Move all of our fixed function fragment color handling to NIR.
This massively reduces our dependency on VC4-specific optimization passes.

shader-db:
total uniforms in shared programs: 32077 -> 32067 (-0.03%)
uniforms in affected programs:     149 -> 139 (-6.71%)
total instructions in shared programs: 98208 -> 98182 (-0.03%)
instructions in affected programs:     2154 -> 2128 (-1.21%)
2015-08-14 11:39:18 -07:00
Eric Anholt 38c6c0f5b4 vc4: Add a helper for making driver-specific NIR load_uniform for GL state
In order to move more of our lowering into NIR, we need the ability to
reference various pipeline state (like texture rectangle scaling factors
or blend colors), so we just set those up as a load_uniform with a big
offset to indicate that it's not within the shader's uniform storage and
is one of our state values.
2015-08-14 11:39:18 -07:00
Eric Anholt d50c182671 nir: Don't try to scalarize unpack ops.
Avoids regressions in vc4 when trying to do our blending in NIR.

v2: Add the other unpack ops I meant to when writing the original commit
    message.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-14 11:39:18 -07:00
Eric Anholt 9e6dc5b64d nir: Add a nir_opt_undef() to handle csels with undef.
We may find a cause to do more undef optimization in the future, but for
now this fixes up things after if flattening.  vc4 was handling this
internally most of the time, but a GLB2.7 shader that did a conditional
discard and assign gl_FragColor in the else was still emitting some extra
code.

total instructions in shared programs: 100809 -> 100795 (-0.01%)
instructions in affected programs:     37 -> 23 (-37.84%)

v2: Use nir_instr_rewrite_src() to update def/use on src[0] (by Thomas
    Helland).
v3: Make sure to flag metadata dirties, and copy the swizzle and abs/neg
    over to src[0], too (by anholt).

Reviewed-by: Thomas Helland <thomashelland90@gmail.com> (v2)
Tested-by: Thomas Helland <thomashelland90@gmail.com> (v2)
2015-08-14 11:39:18 -07:00
Ilia Mirkin b346a84e27 gm107/ir: indirect handle goes first on maxwell also
Fixes fs-simple-texture-size.shader_test

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
2015-08-14 14:11:44 -04:00
Ilia Mirkin 7ff7d5d799 nv30: add depth bounds test support for hw that has it
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-14 13:05:29 -04:00
Ilia Mirkin a6bf20d153 nv50: add depth bounds test support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-14 13:05:29 -04:00
Ilia Mirkin d4087265f6 nvc0: add depth bounds test support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-14 13:05:29 -04:00
Marek Olšák a90aa54fde docs/relnotes: document amdgpu, GL 4.1 and other new features 2015-08-14 15:04:59 +02:00
Marek Olšák 7bfb9ee5ee radeonsi: add all new VI PCI IDs including Fiji 2015-08-14 15:02:31 +02:00
Marek Olšák f47c59322e radeonsi: revert a wrong DB bug workaround for VI
The bug was misunderstood. Besides that, the bug affects a DB feature we
don't use yet.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-14 15:02:31 +02:00
Boyuan Zhang 839bf82606 radeon/uvd: implement HEVC support
add context buffer to fix H265 uvd decode issue.
fix H265 corruption issue caused by incorrect assigned ref_pic_list.

v2: disable interlace for HEVC
    add CZ sps flag workaround
    fix coding style

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-08-14 15:02:31 +02:00
Leo Liu 0654a9ca17 radeon/vce: disable VCE dual instance for harvest part
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:31 +02:00
Leo Liu 09def7e1e0 radeon/vce: implement VCE dual instance support
VCE dual instances are encoding in parallel, it needs two frames for
encoding with their own parameters in one IB. Master instance will check
the task info to find another frame, assign it to the slave instance

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:31 +02:00
Leo Liu 4dfcf6e3a9 radeon/video: config encode stacked frame number based on HW
since VCE 3.0 with dual instances, we need stack frames for them.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Christian König 42bc4e6be4 radeon/vce: make reloc offset signed
We need a negative offset for FW 50.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu 57fabe9f3a radeon/vce: add config task and put task info into encoder v2
The config task has own task ID, extract the configuration functions
into config task.

v2 (chk): calculate offset automatically

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu e91a67abfa radeon/vce: fix VCE fail after rebase
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu fa80c1fe20 radeon/vce: add dual pipe support for VI
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu 468fcdcb4f radeon/vce: add new firmware support for VI and CI
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu 1550790b3f radeon/vce: implement VCE two pipe support
v2: rebase by Marek

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu 22f71dbf79 radeon/uvd: make 30M as minimum for MPEG4 dpb buffer size
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu baecc518c9 radeon/uvd: recalculate dbp buffer size
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu c29f0d4722 radeon/video: add 4K support for decode/encode parameters
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu 261ed77547 gallium/radeon: add h264 performance HW decoder support
v2: -make tonga use new h264 performance HW decoder;
    -integrate it scaling buffer to msg_fb buffer

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00