In changing iris_seqno.[ch] to iris_fine_fence.[ch] and moving the
lines earlier, the newline escape was forgotten.
Fixes: 034329128b ("iris: Rename iris_seqno to iris_fine_fence")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5264>
We should be passing _gt instead of 1 to GEN12_FEATURES or else all TGL
SKUs will be considered as gt1 only.
Fixes: 54996ad492 ("intel/dev: Split .num_subslices out of GEN12_FEATURES macro")
Signed-off-by: Satyeshwar Singh <satyeshwar.singh@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5261>
Fix warning reported by Coverity Scan.
Missing argument to printf format specifier (PRINTF_ARGS)
missing_argument: No argument for format specifier %s.
Fixes: 04c1536bf7 ("r300g: rasterizer debug logging")
Fixes: 85efb2fff0 ("r300g: try to use color varyings for texcoords if max texcoord limit is exceeded")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5274>
This is needed to support the core's usage of coherent buffers for
glVertex-style input. The reason why this was disallowed is that any
mappings will be invalidated. Let the state tracker worry about that,
and just reallocate when we're told.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5276>
Using HALT to immediately jump to the end of the shader is required to
implement GL_EXT_gpu_shader4 and OpenGL 3.0. However, vanilla OpenGL
1.2 doesn't forbid it and it likely makes something somewhere faster.
We should be consistent and implement the same discard behavior on all
hardware if we can.
The rules for HALT on Gen4-5 are a bit different from Gen6+. On the
older hardware, there is no stack for HALT; instead it's up to software
to save and restore mask registers. However, there's no real saving
needed since we only use HALT to jump to the end of the program where
we're about about to do our FB writes. All we need to do is reset AMask
to DMask, the value it was initialized to at the start of the thread.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5244>
If the ~/.cache dir already exists continue on without failing.
Fixes: cd61f5234d ("radv: Handle failing to create .cache dir.")
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5249>
bifrost_sampler_descriptor.zero1 is of type uint8_t.
Fix warning reported by Coverity.
Invalid type in argument to printf format specifier (PRINTF_ARGS)
invalid_type: Argument s->zero1 to format specifier %lx was expected to
have type unsigned long but has type unsigned char.
Fixes: 6148d1be4b ("panfrost: Fix size of bifrost sampler descriptor")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5248>
NV12 is UVUVUV (https://wiki.videolan.org/YUV#NV12) and in Vulkan is
VK_FORMAT_G8_B8R8_2PLANE_420_UNORM. So U=B and V=R. So plane order in
VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM is YUV, which is PIPE_FORMAT_IYUV.
Further confirmation: https://fourcc.org/yuv.php U=Cb V=Cr. From the nir
ycbcr conversion, B=Cb and R=Cr.
Fixes: 75d7ee8029 "util/format: translate 422_UNORM and 420_UNORM vulkan formats"
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5195>
Fix warning reported by Coverity Scan.
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable pq going out of scope leaks the storage it
points to.
Suggested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Fixes: eed5a00989 ("etnaviv: convert perfmon queries to acc queries")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5220>
We're not *quite* ready to open the flood gates on Bifrost (a major
blocker is CI, which is itself blocked on the lockdowns - expected to be
resolved in the coming months..)
Nevertheless, let's add a debug option to probe on compatible Bifrost
devices to avoid keeping out-of-tree patches around.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5272>
Support was dropped and now raises a DATA_INVALID_FAULT on G31. Unknown
if retained on other devices. GL_QUADS is still ok.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
The offsets used for branches need some extra bits twiddled, so add a
field to the clause to indicate this is happening. This is not ambiguous
since a clause can only have a single branch.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
If it's already a register, there's no point in rewriting and it will
disturb the existing register, i.e. for
if (..) {
r0 = vecN ..
} else {
r0 = vecN ..
}
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Figuring out what "shapes" of clauses are kosher happens during
scheduling, not packing, but shouldn't distract the scheduler. So let's
add a new file for these sorts of questions.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>