Commit Graph

98002 Commits

Author SHA1 Message Date
Rob Clark ae44845aff freedreno/ir3: add texture gather support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-11-18 13:39:39 -05:00
Lucas Stach f5d477f447 etnaviv: enable full overwrite when no color buffer is present
The OVERWRITE bit disables destination fetches, which is exactly what
we want when there is no valid color buffer bound.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-11-18 12:33:49 +01:00
Jason Ekstrand 1eab327ba7 i965: Stop including brw_cfg.h in brw_disasm_info.h
The brw_disasm_info header is included by certain tools in order to get
shader assembly from binaries so it's a semi-external header.  Including
brw_cfg.h also pulls in brw_shader.h so you end up getting quite a bit
of our back-end compiler internals.  Instead, make the couple of forward
declarations we need and make the header more stand-alone.  This fixes
the meson build.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 4f82b17287
2017-11-17 21:51:16 -08:00
Jason Ekstrand 0a6a137eb2 i965: Mark BOs as external when we export their handle
Almost all of our BO export paths were already properly marked the BO as
external and added it to the handle table.  Most export use-cases go
through a prime fd or flink where we have a brw_bo export helper that
does the right thing.  The one missing one happens when you call
queryImage and ask for __DRI_IMAGE_ATTRIB_HANDLE.  We just grabbed the
gem handle out of the BO (because it's really easy to do that) and
handed it off to the client; what could go wrong?  As it turns out, this
path is used by basically every compositor that wants to turn around and
call drmModeAddFB2 on it so it can hand it off to display.  The result,
as of 4b1e70cc57, is that we no longer set
MOCS_PTE on those surfaces and the kernel's attempts to disable caching
fail and we scanout gets corruption.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103759
Fixes: 4b1e70cc57
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2017-11-17 17:16:44 -08:00
Jason Ekstrand 344252a27f i965/bufmgr: Add a helper to mark a BO as external
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2017-11-17 17:16:44 -08:00
Andres Gomez 1866f7aee5 i965: Correct disasm_info usage in eu_validate test
Fixes: 4f82b17287 ("i965: Rewrite disassembly annotation code")

Cc: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-11-18 03:07:06 +02:00
Eric Anholt 8d5994098f broadcom/vc5: Set up the padded height at surface creation time.
This centralizes the calculation in the surface, instead of in each
load/store.
2017-11-17 16:09:55 -08:00
Eric Anholt 87391e23cf broadcom/vc5: Ensure that there is always a TLB write.
This should fix some GPU hangs in our (currently always single-threaded)
fragment shaders, and definitely fixes assertion failures in simulation.
2017-11-17 16:09:55 -08:00
Eric Anholt c40ac132e4 broadcom/vc5: Fix clear color for swap_color_rb render targets.
Fixes dEQP-GLES3.functional.depth_stencil_clear.depth.*
2017-11-17 16:09:55 -08:00
Eric Anholt 52f3e9e43c broadcom/vc5: Fix pasteo in front stencil ref value setup.
Fixes piglit masked-clear.
2017-11-17 16:09:55 -08:00
Eric Anholt b63dd626b7 broadcom/vc5: Fix colormasking when we need to swap r/b colors.
Fixes part of piglit masked-clear.
2017-11-17 16:09:55 -08:00
Eric Anholt 2daf941a58 broadcom/vc5: Enable the Z min/max clipping planes. 2017-11-17 16:09:55 -08:00
Eric Anholt c259bf686c broadcom/vc5: Fix driver for new PIPE_SHADER_CAP_MAX_HW_ATOMIC_*. 2017-11-17 16:09:54 -08:00
Brian Paul 2b5b6bebac r300: add PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* switch cases
To silence compiler warnings.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-17 16:09:59 -07:00
Brian Paul af322ed887 tgsi: s/uint/enum pipe_shader_type/
Roland Scheidegger <sroland@vmware.com>
2017-11-17 16:09:40 -07:00
Brian Paul fdee3e1d82 tgsi: bump tgsi_opcode_info::output_mode size to 4 bits
To avoid problems with MSVC.  And verify size with ASSERT_BITFIELD_SIZE().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-17 16:09:39 -07:00
Kenneth Graunke a01ba366e0 i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
This apparently causes hangs on Broadwell, so let's back it out for now.
I think there are other PIPE_CONTROL workarounds that we're missing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
2017-11-17 14:28:22 -08:00
Adam Jackson ddcd4b05a3 egl: Convert int to attrib in eglGetPlatformDisplay
... because converting attrib to int truncates, and that's bad.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-11-17 16:43:16 -05:00
Rob Clark 1831e3fb1d docs: update features for freedreno
Just comparing glxinfo and features.txt, and it seems features.txt is
fairly out of date.  The a5xx specific features (compute/images/atomics/
etc) are recent.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-11-17 15:19:38 -05:00
Matt Turner 821ec473a8 i965: Rename intel_asm_annotation -> brw_disasm_info
It was the only file named intel_* in the compiler.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-17 12:14:38 -08:00
Matt Turner 4f82b17287 i965: Rewrite disassembly annotation code
The old code used an array to store each "instruction group" (the new,
better name than the old overloaded "annotation"), and required a
memmove() to shift elements over in the array when we needed to split a
group so that we could add an error message. This was confusing and
difficult to get right, not the least of which was  because the array
has a tail sentinel not included in .ann_count.

Instead use a linked list, a data structure made for efficient
insertion.

Acked-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-17 12:14:38 -08:00
Matt Turner f80e97346b i965: Simplify annotation_insert_error()
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-17 12:14:38 -08:00
Matt Turner f4276ef7ef i965: Move common code out of #ifdef
I'm going to change the call in a later patch and with the difference in
indentation level it wasn't immediately obvious that the calls were
identical.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-17 12:14:38 -08:00
Anuj Phogat 822fd2341d i965: Remove DWord length from MI_FLUSH_DW definition
Fixes: 6165fda59b ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-17 11:51:28 -08:00
Jason Ekstrand a07f7b2619 anv/cmd_buffer: Take bo_offset into account in fast clear state addresses
Otherwise, if the image is not bound to the start of the buffer, we're
going to be reading and writing its fast clear state in the wrong spot.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2017-11-17 11:32:21 -08:00
Jason Ekstrand a6cc361e5f anv/cmd_buffer: Advance the address when initializing clear colors
Found by inspection

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2017-11-17 11:32:21 -08:00
Boyuan Zhang 3b7fd35d01 radeon/video: enable encode support for raven
Enable h.264 encode for vcn hardware (raven)

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 549a41ed9d radeonsi: enable vcn encode
Enable vcn encode by creating radeon_encoder for vcn.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang fe50797d93 radeon/vcn: add create encoder
Add implementation for create_encoder interface for vcn encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 3c53fbbc87 radeon/vcn: add encode get feedback
Add implementation for get_feedback interface for vcn encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang bc9644460d radeon/vcn: add encode destroy
Add implementation for destroy interface for vcn encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 3f83c24366 radeon/vcn: add encode end frame
Add implementation for end_frame interface for vcn encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 47443bc9f0 radeon/vcn: add encode bitstream
Add implementation for encode_bitstream interface for vcn encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang f40fe728a1 radeon/vcn: add encode begin frame
Add implementation for begin_frame interface for vcn encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang c2448f20a3 radeon/vcn: add encode header implementations
Implement encoding of sps, pps, and silce headers using the newly added h.264
header coding descriptors functions based on h.264 specs.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang d940fdf765 radeon/vcn: add encode header algorithms
Since bitstream headers, e.g. sps, pps, slice, are encoded in driver side, we
need to add corresponding algorithms that required to generate those headers.
According to h.264 specs, signed/unsigned interger Exp-Golomb-coded syntax
element with left bit first (code_se and code_ue) and unsigned integer using
n bits (code_fixed_bits) descriptors function are needed. Therefore, adding
those algorithms and related variables and output algorithms here.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang be996f2213 radeon/vcn: add ib implementations
Implement required ibs and command buffer submission interfaces for vcn encode

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 7f7ae47385 radeon/vcn: add common encode part
Add a skeleton pipe video interface and encode ib interface for video encode
on vcn hardware. Add function defines and structures for vcn encode. Update
Makefile.sources and meson.build with newly added files.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 58aa4dffb4 st/va: implement poc type
pic_order_cnt_type is a required variable when encoding both sps and
slice header, therefore we need to get this value from st, e.g. vaapi
interface, and then pass it to radeon driver for encoding headers.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 76e0dcd5a9 vl: add poc type
Different from vce encoding, vcn encoding requires driver side to encode
bitstream header, such as pps, sps and slice header. pic_order_cnt_type
is a required variable when encoding both sps and slice header, therefore
we need to add this new variable here, and hold the value passed from st,
e.g. vaapi interface

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang c445cdf649 winsys/amdgpu: add vcn enc cs support
New cs support is needed for vcn encode

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang 436a3f8d6d radeon/common: add vcn enc ip info query
New ip info query is needed for vcn encode

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang f2021d92eb radeon/winsys: add vcn enc ring type
New ring type is needed for vcn encode

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Boyuan Zhang d3d8914275 radeon/vcn: add vcn encode interface
Add a new header file for vcn encode interface

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-11-17 12:25:47 -05:00
Gert Wollny b50eda8498 gallium/aux/util/u_surface.c: Silence warnings and remove unneeded MAYBE_UNUSED
* Explicitely convert values to int in comparison.
 * Remove one MAYBE_UNUSED that is actually not needed.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-17 09:27:58 -07:00
Gert Wollny c7bf83ef5c gallium/aux/util/u_debug_image.c: Silence warnings -Wunused-param
Decorate the according parameters with UNUSED.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-17 09:27:58 -07:00
Gert Wollny f23f2146cb gallium/aux/util/u_debug_flush.c: Silence warnings -Wunused-param
Decorate the unused parameters with UNUSED.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-17 09:27:58 -07:00
Gert Wollny 1dca234daf gallium/aux/util/u_debug.c: Silence warnings -Wunused-param
Silence warnings by decoration the parameters with UNUSED.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-17 09:27:57 -07:00
Gert Wollny bec80e892b gallium/aux/util/u_format_table.py: Add UNUSED decoration to the generated function headers
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-17 09:27:57 -07:00
Gert Wollny c7ebf95797 gallium/aux/util/u_async_debug.c: Fix -Wtype-limits warning.
Use size_t instread of unsigned for new_max. realloc later expects
size_t as parameter anyway.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-11-17 09:27:57 -07:00