drm-uapi: Update headers from drm-next
Pull new updates from drm-next as of the following commit: commit a5f2fafece141ef3509e686cea576366d55cabb6 Merge: 71f4e45a4ed3 860433ed2a55 Author: Dave Airlie <airlied@redhat.com> Date: Wed Feb 20 12:16:30 2019 +1000 Merge https://gitlab.freedesktop.org/drm/msm into drm-next Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
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@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
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The last update was done at the following kernel commit :
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commit 78230c46ec0a91dd4256c9e54934b3c7095a7ee3
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Merge: b65bd4031156 037f03155b7d
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commit a5f2fafece141ef3509e686cea576366d55cabb6
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Merge: 71f4e45a4ed3 860433ed2a55
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Author: Dave Airlie <airlied@redhat.com>
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Date: Wed Mar 21 14:07:03 2018 +1000
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Date: Wed Feb 20 12:16:30 2019 +1000
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Merge tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next
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Merge https://gitlab.freedesktop.org/drm/msm into drm-next
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@ -674,6 +674,22 @@ struct drm_get_cap {
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*/
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#define DRM_CLIENT_CAP_ATOMIC 3
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/**
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* DRM_CLIENT_CAP_ASPECT_RATIO
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*
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* If set to 1, the DRM core will provide aspect ratio information in modes.
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*/
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#define DRM_CLIENT_CAP_ASPECT_RATIO 4
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/**
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* DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
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*
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* If set to 1, the DRM core will expose special connectors to be used for
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* writing back to memory the scene setup in the commit. Depends on client
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* also supporting DRM_CLIENT_CAP_ATOMIC
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*/
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#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
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/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
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struct drm_set_client_cap {
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__u64 capability;
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@ -30,11 +30,50 @@
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extern "C" {
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#endif
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/**
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* DOC: overview
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*
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* In the DRM subsystem, framebuffer pixel formats are described using the
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* fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
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* fourcc code, a Format Modifier may optionally be provided, in order to
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* further describe the buffer's format - for example tiling or compression.
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*
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* Format Modifiers
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* ----------------
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*
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* Format modifiers are used in conjunction with a fourcc code, forming a
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* unique fourcc:modifier pair. This format:modifier pair must fully define the
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* format and data layout of the buffer, and should be the only way to describe
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* that particular buffer.
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*
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* Having multiple fourcc:modifier pairs which describe the same layout should
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* be avoided, as such aliases run the risk of different drivers exposing
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* different names for the same data format, forcing userspace to understand
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* that they are aliases.
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*
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* Format modifiers may change any property of the buffer, including the number
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* of planes and/or the required allocation size. Format modifiers are
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* vendor-namespaced, and as such the relationship between a fourcc code and a
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* modifier is specific to the modifer being used. For example, some modifiers
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* may preserve meaning - such as number of planes - from the fourcc code,
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* whereas others may not.
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*
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* Vendors should document their modifier usage in as much detail as
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* possible, to ensure maximum compatibility across devices, drivers and
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* applications.
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*
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* The authoritative list of format modifier codes is found in
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* `include/uapi/drm/drm_fourcc.h`
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*/
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#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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((__u32)(c) << 16) | ((__u32)(d) << 24))
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#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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/* Reserve 0 for the invalid format specifier */
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#define DRM_FORMAT_INVALID 0
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/* color index */
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#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
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@ -112,6 +151,21 @@ extern "C" {
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#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
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#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
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#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
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/*
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* packed YCbCr420 2x2 tiled formats
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* first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
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*/
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/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
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#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
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/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
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#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
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/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
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#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
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/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
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#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
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/*
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* 2 plane RGB + A
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@ -141,6 +195,27 @@ extern "C" {
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#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [10:6] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
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*/
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#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [12:4] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
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*/
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#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
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*/
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#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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@ -183,6 +258,9 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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/* add more to the end as needed */
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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@ -298,6 +376,15 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/*
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* Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
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*
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* This is a simple tiled layout using tiles of 16x16 pixels in a row-major
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* layout. For YCbCr formats Cb/Cr components are taken in such a way that
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* they correspond to their 16x16 luma block.
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
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/*
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* Qualcomm Compressed Format
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*
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* Pixel data height is aligned with macrotile height.
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* Entire pixel data buffer is aligned with 4k(bytes).
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*/
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#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
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#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
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/* Vivante framebuffer modifiers */
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*/
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#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
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/*
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* Arm Framebuffer Compression (AFBC) modifiers
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*
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* AFBC is a proprietary lossless image compression protocol and format.
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* It provides fine-grained random access and minimizes the amount of data
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* transferred between IP blocks.
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*
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* AFBC has several features which may be supported and/or used, which are
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* represented using bits in the modifier. Not all combinations are valid,
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* and different devices or use-cases may support different combinations.
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*
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* Further information on the use of AFBC modifiers can be found in
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* Documentation/gpu/afbc.rst
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*/
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#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
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/*
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* AFBC superblock size
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*
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* Indicates the superblock size(s) used for the AFBC buffer. The buffer
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* size (in pixels) must be aligned to a multiple of the superblock size.
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* Four lowest significant bits(LSBs) are reserved for block size.
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*
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* Where one superblock size is specified, it applies to all planes of the
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* buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
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* the first applies to the Luma plane and the second applies to the Chroma
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* plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
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* Multiple superblock sizes are only valid for multi-plane YCbCr formats.
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*/
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
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#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
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/*
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* AFBC lossless colorspace transform
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*
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* Indicates that the buffer makes use of the AFBC lossless colorspace
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* transform.
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*/
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#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
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/*
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* AFBC block-split
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*
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* Indicates that the payload of each superblock is split. The second
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* half of the payload is positioned at a predefined offset from the start
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* of the superblock payload.
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*/
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#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
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/*
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* AFBC sparse layout
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*
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* This flag indicates that the payload of each superblock must be stored at a
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* predefined position relative to the other superblocks in the same AFBC
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* buffer. This order is the same order used by the header buffer. In this mode
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* each superblock is given the same amount of space as an uncompressed
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* superblock of the particular format would require, rounding up to the next
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* multiple of 128 bytes in size.
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*/
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#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
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/*
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* AFBC copy-block restrict
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*
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* Buffers with this flag must obey the copy-block restriction. The restriction
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* is such that there are no copy-blocks referring across the border of 8x8
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* blocks. For the subsampled data the 8x8 limitation is also subsampled.
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*/
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#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
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/*
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* AFBC tiled layout
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*
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* The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
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* superblocks inside a tile are stored together in memory. 8x8 tiles are used
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* for pixel formats up to and including 32 bpp while 4x4 tiles are used for
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* larger bpp formats. The order between the tiles is scan line.
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* When the tiled layout is used, the buffer size (in pixels) must be aligned
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* to the tile size.
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*/
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#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
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/*
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* AFBC solid color blocks
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*
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* Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
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* can be reduced if a whole superblock is a single color.
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*/
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#define AFBC_FORMAT_MOD_SC (1ULL << 9)
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/*
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* AFBC double-buffer
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*
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* Indicates that the buffer is allocated in a layout safe for front-buffer
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* rendering.
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*/
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#define AFBC_FORMAT_MOD_DB (1ULL << 10)
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/*
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* AFBC buffer content hints
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*
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* Indicates that the buffer includes per-superblock content hints.
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*/
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#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
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/*
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* Allwinner tiled modifier
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*
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* This tiling mode is implemented by the VPU found on all Allwinner platforms,
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* codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
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* planes.
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*
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* With this tiling, the luminance samples are disposed in tiles representing
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* 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
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* The pixel order in each tile is linear and the tiles are disposed linearly,
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* both in row-major order.
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*/
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#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
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#if defined(__cplusplus)
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}
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#endif
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#define DRM_MODE_PICTURE_ASPECT_NONE 0
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#define DRM_MODE_PICTURE_ASPECT_4_3 1
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#define DRM_MODE_PICTURE_ASPECT_16_9 2
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#define DRM_MODE_PICTURE_ASPECT_64_27 3
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#define DRM_MODE_PICTURE_ASPECT_256_135 4
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/* Content type options */
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#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
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#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
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#define DRM_MODE_CONTENT_TYPE_PHOTO 2
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#define DRM_MODE_CONTENT_TYPE_CINEMA 3
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#define DRM_MODE_CONTENT_TYPE_GAME 4
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/* Aspect ratio flag bitmask (4 bits 22:19) */
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#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
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(DRM_MODE_PICTURE_ASPECT_4_3<<19)
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#define DRM_MODE_FLAG_PIC_AR_16_9 \
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(DRM_MODE_PICTURE_ASPECT_16_9<<19)
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#define DRM_MODE_FLAG_PIC_AR_64_27 \
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(DRM_MODE_PICTURE_ASPECT_64_27<<19)
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#define DRM_MODE_FLAG_PIC_AR_256_135 \
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(DRM_MODE_PICTURE_ASPECT_256_135<<19)
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#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
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DRM_MODE_FLAG_NHSYNC | \
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/*
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* DRM_MODE_REFLECT_<axis>
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*
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* Signals that the contents of a drm plane is reflected in the <axis> axis,
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* Signals that the contents of a drm plane is reflected along the <axis> axis,
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* in the same way as mirroring.
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* See kerneldoc chapter "Plane Composition Properties" for more details.
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*
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* This define is provided as a convenience, looking up the property id
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* using the name->prop id lookup is the preferred method.
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@ -338,6 +352,7 @@ enum drm_mode_subconnector {
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#define DRM_MODE_CONNECTOR_VIRTUAL 15
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#define DRM_MODE_CONNECTOR_DSI 16
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#define DRM_MODE_CONNECTOR_DPI 17
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#define DRM_MODE_CONNECTOR_WRITEBACK 18
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struct drm_mode_get_connector {
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@ -873,6 +888,25 @@ struct drm_mode_revoke_lease {
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__u32 lessee_id;
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};
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/**
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* struct drm_mode_rect - Two dimensional rectangle.
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* @x1: Horizontal starting coordinate (inclusive).
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* @y1: Vertical starting coordinate (inclusive).
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* @x2: Horizontal ending coordinate (exclusive).
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* @y2: Vertical ending coordinate (exclusive).
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*
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* With drm subsystem using struct drm_rect to manage rectangular area this
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* export it to user-space.
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*
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* Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.
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*/
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struct drm_mode_rect {
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__s32 x1;
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__s32 y1;
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__s32 x2;
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__s32 y2;
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};
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#if defined(__cplusplus)
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}
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#endif
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@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait {
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int irq_seq;
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} drm_i915_irq_wait_t;
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/*
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* Different modes of per-process Graphics Translation Table,
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* see I915_PARAM_HAS_ALIASING_PPGTT
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*/
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#define I915_GEM_PPGTT_NONE 0
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#define I915_GEM_PPGTT_ALIASING 1
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#define I915_GEM_PPGTT_FULL 2
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/* Ioctl to query kernel params:
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*/
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#define I915_PARAM_IRQ_ACTIVE 1
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@ -529,6 +537,28 @@ typedef struct drm_i915_irq_wait {
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*/
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||||
#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
|
||||
|
||||
/*
|
||||
* Once upon a time we supposed that writes through the GGTT would be
|
||||
* immediately in physical memory (once flushed out of the CPU path). However,
|
||||
* on a few different processors and chipsets, this is not necessarily the case
|
||||
* as the writes appear to be buffered internally. Thus a read of the backing
|
||||
* storage (physical memory) via a different path (with different physical tags
|
||||
* to the indirect write via the GGTT) will see stale values from before
|
||||
* the GGTT write. Inside the kernel, we can for the most part keep track of
|
||||
* the different read/write domains in use (e.g. set-domain), but the assumption
|
||||
* of coherency is baked into the ABI, hence reporting its true state in this
|
||||
* parameter.
|
||||
*
|
||||
* Reports true when writes via mmap_gtt are immediately visible following an
|
||||
* lfence to flush the WCB.
|
||||
*
|
||||
* Reports false when writes via mmap_gtt are indeterminately delayed in an in
|
||||
* internal buffer and are _not_ immediately visible to third parties accessing
|
||||
* directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
|
||||
* communications channel when reporting false is strongly disadvised.
|
||||
*/
|
||||
#define I915_PARAM_MMAP_GTT_COHERENT 52
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
__s32 param;
|
||||
/*
|
||||
|
@ -1456,9 +1486,73 @@ struct drm_i915_gem_context_param {
|
|||
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
|
||||
#define I915_CONTEXT_DEFAULT_PRIORITY 0
|
||||
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
|
||||
/*
|
||||
* When using the following param, value should be a pointer to
|
||||
* drm_i915_gem_context_param_sseu.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_SSEU 0x7
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* Context SSEU programming
|
||||
*
|
||||
* It may be necessary for either functional or performance reason to configure
|
||||
* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
|
||||
* Sub-slice/EU).
|
||||
*
|
||||
* This is done by configuring SSEU configuration using the below
|
||||
* @struct drm_i915_gem_context_param_sseu for every supported engine which
|
||||
* userspace intends to use.
|
||||
*
|
||||
* Not all GPUs or engines support this functionality in which case an error
|
||||
* code -ENODEV will be returned.
|
||||
*
|
||||
* Also, flexibility of possible SSEU configuration permutations varies between
|
||||
* GPU generations and software imposed limitations. Requesting such a
|
||||
* combination will return an error code of -EINVAL.
|
||||
*
|
||||
* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
|
||||
* favour of a single global setting.
|
||||
*/
|
||||
struct drm_i915_gem_context_param_sseu {
|
||||
/*
|
||||
* Engine class & instance to be configured or queried.
|
||||
*/
|
||||
__u16 engine_class;
|
||||
__u16 engine_instance;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/*
|
||||
* Mask of slices to enable for the context. Valid values are a subset
|
||||
* of the bitmask value returned for I915_PARAM_SLICE_MASK.
|
||||
*/
|
||||
__u64 slice_mask;
|
||||
|
||||
/*
|
||||
* Mask of subslices to enable for the context. Valid values are a
|
||||
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
|
||||
*/
|
||||
__u64 subslice_mask;
|
||||
|
||||
/*
|
||||
* Minimum/Maximum number of EUs to enable per subslice for the
|
||||
* context. min_eus_per_subslice must be inferior or equal to
|
||||
* max_eus_per_subslice.
|
||||
*/
|
||||
__u16 min_eus_per_subslice;
|
||||
__u16 max_eus_per_subslice;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 rsvd;
|
||||
};
|
||||
|
||||
enum drm_i915_oa_format {
|
||||
I915_OA_FORMAT_A13 = 1, /* HSW only */
|
||||
I915_OA_FORMAT_A29, /* HSW only */
|
||||
|
|
|
@ -32,143 +32,615 @@ extern "C" {
|
|||
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
|
||||
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_create {
|
||||
/**
|
||||
* @size:
|
||||
*
|
||||
* The size, in bytes, of the buffer object to be created.
|
||||
*/
|
||||
__u64 size;
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* A bitmask of flags that influence the creation of GEM objects:
|
||||
*
|
||||
* DRM_TEGRA_GEM_CREATE_TILED
|
||||
* Use the 16x16 tiling format for this buffer.
|
||||
*
|
||||
* DRM_TEGRA_GEM_CREATE_BOTTOM_UP
|
||||
* The buffer has a bottom-up layout.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* The handle of the created GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_mmap {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle of the GEM object to obtain an mmap offset for.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* The mmap offset for the given GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_read {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to read the current value from.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The current syncpoint value. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_incr {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to increment.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_wait {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to wait on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to wait.
|
||||
*/
|
||||
__u32 thresh;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, to wait.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The new syncpoint value after the wait. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_open_channel - parameters for the open channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_open_channel {
|
||||
/**
|
||||
* @client:
|
||||
*
|
||||
* The client ID for this channel.
|
||||
*/
|
||||
__u32 client;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. Set by the kernel upon
|
||||
* successful completion of the IOCTL. This context needs to be passed
|
||||
* to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_close_channel - parameters for the close channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_close_channel {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. This is obtained from the
|
||||
* DRM_TEGRA_OPEN_CHANNEL IOCTL.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel for which to obtain
|
||||
* the syncpoint ID.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @index:
|
||||
*
|
||||
* Index of the client syncpoint for which to obtain the ID.
|
||||
*/
|
||||
__u32 index;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the given syncpoint. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt_base {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying for which channel to obtain the
|
||||
* wait base.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint for which to obtain the wait base.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the wait base corresponding to the client syncpoint. Set
|
||||
* by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt - syncpoint increment operation
|
||||
*/
|
||||
struct drm_tegra_syncpt {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to operate on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @incrs:
|
||||
*
|
||||
* Number of increments to perform for the syncpoint.
|
||||
*/
|
||||
__u32 incrs;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_cmdbuf - structure describing a command buffer
|
||||
*/
|
||||
struct drm_tegra_cmdbuf {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to a GEM object containing the command buffer.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, into the GEM object identified by @handle at
|
||||
* which the command buffer starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @words:
|
||||
*
|
||||
* Number of 32-bit words in this command buffer.
|
||||
*/
|
||||
__u32 words;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_reloc - GEM object relocation structure
|
||||
*/
|
||||
struct drm_tegra_reloc {
|
||||
struct {
|
||||
/**
|
||||
* @cmdbuf.handle:
|
||||
*
|
||||
* Handle to the GEM object containing the command buffer for
|
||||
* which to perform this GEM object relocation.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @cmdbuf.offset:
|
||||
*
|
||||
* Offset, in bytes, into the command buffer at which to
|
||||
* insert the relocated address.
|
||||
*/
|
||||
__u32 offset;
|
||||
} cmdbuf;
|
||||
struct {
|
||||
/**
|
||||
* @target.handle:
|
||||
*
|
||||
* Handle to the GEM object to be relocated.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @target.offset:
|
||||
*
|
||||
* Offset, in bytes, into the target GEM object at which the
|
||||
* relocated data starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
} target;
|
||||
|
||||
/**
|
||||
* @shift:
|
||||
*
|
||||
* The number of bits by which to shift relocated addresses.
|
||||
*/
|
||||
__u32 shift;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_waitchk - wait check structure
|
||||
*/
|
||||
struct drm_tegra_waitchk {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object containing a command stream on which to
|
||||
* perform the wait check.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, of the location in the command stream to perform
|
||||
* the wait check on.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint to wait check.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to check.
|
||||
*/
|
||||
__u32 thresh;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_submit - job submission structure
|
||||
*/
|
||||
struct drm_tegra_submit {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel to use for the
|
||||
* execution of this job.
|
||||
*/
|
||||
__u64 context;
|
||||
__u32 num_syncpts;
|
||||
__u32 num_cmdbufs;
|
||||
__u32 num_relocs;
|
||||
__u32 num_waitchks;
|
||||
__u32 waitchk_mask;
|
||||
__u32 timeout;
|
||||
__u64 syncpts;
|
||||
__u64 cmdbufs;
|
||||
__u64 relocs;
|
||||
__u64 waitchks;
|
||||
__u32 fence; /* Return value */
|
||||
|
||||
__u32 reserved[5]; /* future expansion */
|
||||
/**
|
||||
* @num_syncpts:
|
||||
*
|
||||
* The number of syncpoints operated on by this job. This defines the
|
||||
* length of the array pointed to by @syncpts.
|
||||
*/
|
||||
__u32 num_syncpts;
|
||||
|
||||
/**
|
||||
* @num_cmdbufs:
|
||||
*
|
||||
* The number of command buffers to execute as part of this job. This
|
||||
* defines the length of the array pointed to by @cmdbufs.
|
||||
*/
|
||||
__u32 num_cmdbufs;
|
||||
|
||||
/**
|
||||
* @num_relocs:
|
||||
*
|
||||
* The number of relocations to perform before executing this job.
|
||||
* This defines the length of the array pointed to by @relocs.
|
||||
*/
|
||||
__u32 num_relocs;
|
||||
|
||||
/**
|
||||
* @num_waitchks:
|
||||
*
|
||||
* The number of wait checks to perform as part of this job. This
|
||||
* defines the length of the array pointed to by @waitchks.
|
||||
*/
|
||||
__u32 num_waitchks;
|
||||
|
||||
/**
|
||||
* @waitchk_mask:
|
||||
*
|
||||
* Bitmask of valid wait checks.
|
||||
*/
|
||||
__u32 waitchk_mask;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, before this job is cancelled.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @syncpts:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_syncpt structures that
|
||||
* specify the syncpoint operations performed as part of this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_syncpts.
|
||||
*/
|
||||
__u64 syncpts;
|
||||
|
||||
/**
|
||||
* @cmdbufs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_cmdbuf structures that
|
||||
* define the command buffers to execute as part of this job. The
|
||||
* number of elements in the array must be equal to the value given
|
||||
* by @num_syncpts.
|
||||
*/
|
||||
__u64 cmdbufs;
|
||||
|
||||
/**
|
||||
* @relocs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_reloc structures that
|
||||
* specify the relocations that need to be performed before executing
|
||||
* this job. The number of elements in the array must be equal to the
|
||||
* value given by @num_relocs.
|
||||
*/
|
||||
__u64 relocs;
|
||||
|
||||
/**
|
||||
* @waitchks:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_waitchk structures that
|
||||
* specify the wait checks to be performed while executing this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_waitchks.
|
||||
*/
|
||||
__u64 waitchks;
|
||||
|
||||
/**
|
||||
* @fence:
|
||||
*
|
||||
* The threshold of the syncpoint associated with this job after it
|
||||
* has been completed. Set by the kernel upon successful completion of
|
||||
* the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
|
||||
* wait for this job to be finished.
|
||||
*/
|
||||
__u32 fence;
|
||||
|
||||
/**
|
||||
* @reserved:
|
||||
*
|
||||
* This field is reserved for future use. Must be 0.
|
||||
*/
|
||||
__u32 reserved[5];
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode to set. Must be one of:
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_PITCH
|
||||
* pitch linear format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_TILED
|
||||
* 16x16 tiling format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_BLOCK
|
||||
* 16Bx2 tiling format
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The value to set for the tiling mode parameter.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode currently associated with the GEM object. Set by
|
||||
* the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The tiling mode parameter currently associated with the GEM object.
|
||||
* Set by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
|
||||
#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags to set for the GEM object.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags currently associated with the GEM object. Set by the
|
||||
* kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
|
@ -193,7 +665,7 @@ struct drm_tegra_gem_get_flags {
|
|||
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
|
||||
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
|
||||
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
|
||||
|
|
|
@ -52,6 +52,14 @@ extern "C" {
|
|||
*
|
||||
* This asks the kernel to have the GPU execute an optional binner
|
||||
* command list, and a render command list.
|
||||
*
|
||||
* The L1T, slice, L2C, L2T, and GCA caches will be flushed before
|
||||
* each CL executes. The VCD cache should be flushed (if necessary)
|
||||
* by the submitted CLs. The TLB writes are guaranteed to have been
|
||||
* flushed by the time the render done IRQ happens, which is the
|
||||
* trigger for out_sync. Any dirtying of cachelines by the job (only
|
||||
* possible using TMU writes) must be flushed by the caller using the
|
||||
* CL's cache flush commands.
|
||||
*/
|
||||
struct drm_v3d_submit_cl {
|
||||
/* Pointer to the binner command list.
|
||||
|
|
Loading…
Reference in New Issue