radeonsi: rename r600_resource to si_resource
Also split it into seperate header and add some helper functions. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
parent
dcf8754cce
commit
fe41287ffa
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@ -30,6 +30,8 @@
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#include "util/u_double_list.h"
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#include "util/u_transfer.h"
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#include "radeonsi_resource.h"
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#define R600_ERR(fmt, args...) \
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fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
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@ -55,17 +57,6 @@ struct r600_tiling_info {
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unsigned group_bytes;
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};
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struct r600_resource {
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struct u_resource b;
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/* Winsys objects. */
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struct pb_buffer *buf;
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struct radeon_winsys_cs_handle *cs_buf;
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/* Resource state. */
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unsigned domains;
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};
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/* R600/R700 STATES */
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struct r600_query {
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union {
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@ -85,7 +76,7 @@ struct r600_query {
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/* The buffer where query results are stored. It's used as a ring,
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* data blocks for current query are stored sequentially from
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* results_start to results_end, with wrapping on the buffer end */
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struct r600_resource *buffer;
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struct si_resource *buffer;
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/* The number of dwords for begin_query or end_query. */
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unsigned num_cs_dw;
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/* linked list of queries */
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@ -96,7 +87,7 @@ struct r600_so_target {
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struct pipe_stream_output_target b;
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/* The buffer where BUFFER_FILLED_SIZE is stored. */
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struct r600_resource *filled_size;
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struct si_resource *filled_size;
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unsigned stride;
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unsigned so_index;
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};
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@ -113,7 +104,7 @@ struct r600_draw {
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uint32_t indices_bo_offset;
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unsigned db_render_override;
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unsigned db_render_control;
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struct r600_resource *indices;
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struct si_resource *indices;
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};
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struct r600_context;
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@ -133,7 +124,7 @@ void r600_context_queries_suspend(struct r600_context *ctx);
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void r600_context_queries_resume(struct r600_context *ctx);
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void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
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int flag_wait);
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void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
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void r600_context_emit_fence(struct r600_context *ctx, struct si_resource *fence,
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unsigned offset, unsigned value);
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void r600_context_streamout_begin(struct r600_context *ctx);
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@ -40,7 +40,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
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struct pipe_resource *buf)
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{
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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struct r600_resource *rbuffer = r600_resource(buf);
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struct si_resource *rbuffer = si_resource(buf);
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pb_reference(&rbuffer->buf, NULL);
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FREE(rbuffer);
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@ -72,7 +72,7 @@ static struct pipe_transfer *r600_get_transfer(struct pipe_context *ctx,
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static void *r600_buffer_transfer_map(struct pipe_context *pipe,
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struct pipe_transfer *transfer)
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{
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struct r600_resource *rbuffer = r600_resource(transfer->resource);
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struct si_resource *rbuffer = si_resource(transfer->resource);
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struct r600_context *rctx = (struct r600_context*)pipe;
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uint8_t *data;
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@ -115,7 +115,7 @@ static const struct u_resource_vtbl r600_buffer_vtbl =
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};
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bool r600_init_resource(struct r600_screen *rscreen,
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struct r600_resource *res,
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struct si_resource *res,
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unsigned size, unsigned alignment,
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unsigned bind, unsigned usage)
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{
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@ -160,11 +160,11 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
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const struct pipe_resource *templ)
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{
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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struct r600_resource *rbuffer;
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struct si_resource *rbuffer;
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/* XXX We probably want a different alignment for buffers and textures. */
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unsigned alignment = 4096;
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rbuffer = MALLOC_STRUCT(r600_resource);
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rbuffer = MALLOC_STRUCT(si_resource);
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rbuffer->b.b = *templ;
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pipe_reference_init(&rbuffer->b.b.reference, 1);
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@ -185,7 +185,7 @@ void r600_upload_index_buffer(struct r600_context *rctx,
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ib->user_buffer, &ib->offset, &ib->buffer);
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}
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void r600_upload_const_buffer(struct r600_context *rctx, struct r600_resource **rbuffer,
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void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer,
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const uint8_t *ptr, unsigned size,
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uint32_t *const_offset)
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{
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@ -36,7 +36,7 @@
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void r600_get_backend_mask(struct r600_context *ctx)
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{
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struct radeon_winsys_cs *cs = ctx->cs;
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struct r600_resource *buffer;
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struct si_resource *buffer;
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uint32_t *results;
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unsigned num_backends = ctx->screen->info.r600_num_backends;
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unsigned i, mask = 0;
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@ -66,9 +66,9 @@ void r600_get_backend_mask(struct r600_context *ctx)
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/* otherwise backup path for older kernels */
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/* create buffer for event data */
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buffer = (struct r600_resource*)
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pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
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PIPE_USAGE_STAGING, ctx->max_db*16);
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buffer = si_resource_create_custom(&ctx->screen->screen,
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PIPE_USAGE_STAGING,
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ctx->max_db*16);
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if (!buffer)
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goto err;
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@ -102,7 +102,7 @@ void r600_get_backend_mask(struct r600_context *ctx)
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}
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}
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pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
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si_resource_reference(&buffer, NULL);
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if (mask != 0) {
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ctx->backend_mask = mask;
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@ -256,7 +256,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
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si_pm4_reset_emitted(ctx);
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}
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void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
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void r600_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value)
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{
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struct radeon_winsys_cs *cs = ctx->cs;
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uint64_t va;
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@ -594,8 +594,9 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned
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* being written by the gpu, hence staging is probably a good
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* usage pattern.
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*/
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query->buffer = (struct r600_resource*)
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pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size);
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query->buffer = si_resource_create_custom(&ctx->screen->screen,
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PIPE_USAGE_STAGING,
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buffer_size);
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if (!query->buffer) {
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FREE(query);
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return NULL;
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@ -605,7 +606,7 @@ struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned
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void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
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{
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pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL);
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si_resource_reference(&query->buffer, NULL);
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free(query);
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}
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@ -709,7 +710,7 @@ void r600_context_streamout_begin(struct r600_context *ctx)
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cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
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cs->buf[cs->cdw++] =
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r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
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r600_context_bo_reloc(ctx, si_resource(t[i]->b.buffer),
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RADEON_USAGE_WRITE);
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if (ctx->streamout_append_bitmask & (1 << i)) {
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@ -831,7 +832,7 @@ void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_tar
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cs->buf[cs->cdw++] = t->b.buffer_offset >> 2;
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cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
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cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, (struct r600_resource*)t->b.buffer,
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cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, (struct si_resource*)t->b.buffer,
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RADEON_USAGE_WRITE);
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cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
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@ -47,7 +47,7 @@ void evergreen_flush_vgt_streamout(struct r600_context *ctx);
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void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit);
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static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
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static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct si_resource *rbo,
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enum radeon_bo_usage usage)
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{
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assert(usage);
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@ -39,7 +39,7 @@ struct r600_transfer {
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};
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struct r600_resource_texture {
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struct r600_resource resource;
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struct si_resource resource;
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/* If this resource is a depth-stencil buffer on evergreen, this contains
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* the depth part of the format. There is a separate stencil resource
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@ -77,11 +77,6 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
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const struct pipe_resource *base,
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struct winsys_handle *whandle);
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static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
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{
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return (struct r600_resource*)r;
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}
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int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource *texture, boolean just_create);
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/* r600_texture.c texture transfer functions. */
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@ -99,7 +94,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
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struct r600_context;
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void r600_upload_const_buffer(struct r600_context *rctx, struct r600_resource **rbuffer,
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void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer,
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const uint8_t *ptr, unsigned size,
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uint32_t *const_offset);
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@ -456,7 +456,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
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struct winsys_handle *whandle)
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{
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
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struct r600_resource *resource = &rtex->resource;
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struct si_resource *resource = &rtex->resource;
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struct radeon_surface *surface = &rtex->surface;
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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@ -480,13 +480,13 @@ static void r600_texture_destroy(struct pipe_screen *screen,
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struct pipe_resource *ptex)
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{
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
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struct r600_resource *resource = &rtex->resource;
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struct si_resource *resource = &rtex->resource;
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if (rtex->flushed_depth_texture)
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pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
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si_resource_reference(&rtex->flushed_depth_texture, NULL);
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if (rtex->stencil)
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pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
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si_resource_reference(&rtex->stencil, NULL);
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pb_reference(&resource->buf, NULL);
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FREE(rtex);
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@ -515,7 +515,7 @@ r600_texture_create_object(struct pipe_screen *screen,
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struct radeon_surface *surface)
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{
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struct r600_resource_texture *rtex;
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struct r600_resource *resource;
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struct si_resource *resource;
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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int r;
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@ -563,7 +563,7 @@ r600_texture_create_object(struct pipe_screen *screen,
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base_align = rtex->surface.bo_alignment;
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if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
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pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
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si_resource_reference(&rtex->stencil, NULL);
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FREE(rtex);
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return NULL;
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}
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@ -877,14 +877,14 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
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char *map;
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if (rtransfer->staging_texture) {
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buf = ((struct r600_resource *)rtransfer->staging_texture)->cs_buf;
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buf = si_resource(rtransfer->staging_texture)->cs_buf;
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} else {
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
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if (rtex->flushed_depth_texture)
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buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
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buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
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else
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buf = ((struct r600_resource *)transfer->resource)->cs_buf;
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buf = si_resource(transfer->resource)->cs_buf;
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offset = rtransfer->offset +
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transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
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@ -906,14 +906,14 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
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struct radeon_winsys_cs_handle *buf;
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if (rtransfer->staging_texture) {
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buf = ((struct r600_resource *)rtransfer->staging_texture)->cs_buf;
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buf = si_resource(rtransfer->staging_texture)->cs_buf;
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} else {
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
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if (rtex->flushed_depth_texture) {
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buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
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buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
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} else {
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buf = ((struct r600_resource *)transfer->resource)->cs_buf;
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buf = si_resource(transfer->resource)->cs_buf;
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}
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}
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rctx->ws->buffer_unmap(buf);
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@ -61,9 +61,9 @@ static struct r600_fence *r600_create_fence(struct r600_context *rctx)
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if (!rscreen->fences.bo) {
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/* Create the shared buffer object */
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rscreen->fences.bo = (struct r600_resource*)
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pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
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PIPE_USAGE_STAGING, 4096);
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rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
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PIPE_USAGE_STAGING,
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4096);
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if (!rscreen->fences.bo) {
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R600_ERR("r600: failed to create bo for fence objects\n");
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goto out;
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@ -119,9 +119,8 @@ static struct r600_fence *r600_create_fence(struct r600_context *rctx)
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r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
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/* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
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fence->sleep_bo = (struct r600_resource*)
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pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
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PIPE_USAGE_STAGING, 1);
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fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
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/* Add the fence as a dummy relocation. */
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r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
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@ -495,7 +494,7 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
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}
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rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
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pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
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si_resource_reference(&rscreen->fences.bo, NULL);
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}
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pipe_mutex_destroy(rscreen->fences.mutex);
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@ -513,7 +512,7 @@ static void r600_fence_reference(struct pipe_screen *pscreen,
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if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
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struct r600_screen *rscreen = (struct r600_screen *)pscreen;
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pipe_mutex_lock(rscreen->fences.mutex);
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pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
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si_resource_reference(&(*oldf)->sleep_bo, NULL);
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LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
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pipe_mutex_unlock(rscreen->fences.mutex);
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}
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@ -75,7 +75,7 @@ struct r600_atom_surface_sync {
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};
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struct r600_pipe_fences {
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struct r600_resource *bo;
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struct si_resource *bo;
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unsigned *data;
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unsigned next_index;
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/* linked list of preallocated blocks */
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@ -120,7 +120,7 @@ struct r600_textures_info {
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struct r600_fence {
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struct pipe_reference reference;
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unsigned index; /* in the shared bo */
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struct r600_resource *sleep_bo;
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struct si_resource *sleep_bo;
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struct list_head head;
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};
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@ -239,7 +239,7 @@ void r600_flush_depth_textures(struct r600_context *rctx);
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/* r600_buffer.c */
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bool r600_init_resource(struct r600_screen *rscreen,
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struct r600_resource *res,
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struct si_resource *res,
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unsigned size, unsigned alignment,
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unsigned bind, unsigned usage);
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struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
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@ -323,7 +323,7 @@ static INLINE unsigned r600_pack_float_12p4(float x)
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static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
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{
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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struct r600_resource *rresource = (struct r600_resource*)resource;
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struct si_resource *rresource = (struct si_resource*)resource;
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return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
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||||
}
|
||||
|
|
|
@ -69,14 +69,13 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
|
|||
}
|
||||
|
||||
void si_pm4_add_bo(struct si_pm4_state *state,
|
||||
struct r600_resource *bo,
|
||||
struct si_resource *bo,
|
||||
enum radeon_bo_usage usage)
|
||||
{
|
||||
unsigned idx = state->nbo++;
|
||||
assert(idx < SI_PM4_MAX_BO);
|
||||
|
||||
pipe_resource_reference((struct pipe_resource**)&state->bo[idx],
|
||||
(struct pipe_resource*)bo);
|
||||
si_resource_reference(&state->bo[idx], bo);
|
||||
state->bo_usage[idx] = usage;
|
||||
}
|
||||
|
||||
|
@ -120,8 +119,7 @@ void si_pm4_free_state(struct r600_context *rctx,
|
|||
}
|
||||
|
||||
for (int i = 0; i < state->nbo; ++i) {
|
||||
pipe_resource_reference((struct pipe_resource**)&state->bo[idx],
|
||||
NULL);
|
||||
si_resource_reference(&state->bo[idx], NULL);
|
||||
}
|
||||
FREE(state);
|
||||
}
|
||||
|
|
|
@ -51,13 +51,13 @@ struct si_pm4_state
|
|||
|
||||
/* BO's referenced by this state */
|
||||
unsigned nbo;
|
||||
struct r600_resource *bo[SI_PM4_MAX_BO];
|
||||
struct si_resource *bo[SI_PM4_MAX_BO];
|
||||
enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
|
||||
};
|
||||
|
||||
void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
|
||||
void si_pm4_add_bo(struct si_pm4_state *state,
|
||||
struct r600_resource *bo,
|
||||
struct si_resource *bo,
|
||||
enum radeon_bo_usage usage);
|
||||
|
||||
void si_pm4_inval_shader_cache(struct si_pm4_state *state);
|
||||
|
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
* license, and/or sell copies of the Software, and to permit persons to whom
|
||||
* the Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Christian König <christian.koenig@amd.com>
|
||||
*/
|
||||
|
||||
#ifndef RADEONSI_RESOURCE_H
|
||||
#define RADEONSI_RESOURCE_H
|
||||
|
||||
#include "../../winsys/radeon/drm/radeon_winsys.h"
|
||||
#include "util/u_transfer.h"
|
||||
#include "util/u_inlines.h"
|
||||
|
||||
struct si_resource {
|
||||
struct u_resource b;
|
||||
|
||||
/* Winsys objects. */
|
||||
struct pb_buffer *buf;
|
||||
struct radeon_winsys_cs_handle *cs_buf;
|
||||
|
||||
/* Resource state. */
|
||||
unsigned domains;
|
||||
};
|
||||
|
||||
static INLINE void
|
||||
si_resource_reference(struct si_resource **ptr, struct si_resource *res)
|
||||
{
|
||||
pipe_resource_reference((struct pipe_resource **)ptr,
|
||||
(struct pipe_resource *)res);
|
||||
}
|
||||
|
||||
static INLINE struct si_resource *
|
||||
si_resource(struct pipe_resource *r)
|
||||
{
|
||||
return (struct si_resource*)r;
|
||||
}
|
||||
|
||||
static INLINE struct si_resource *
|
||||
si_resource_create_custom(struct pipe_screen *screen,
|
||||
unsigned usage, unsigned size)
|
||||
{
|
||||
assert(size);
|
||||
return si_resource(pipe_buffer_create(screen,
|
||||
PIPE_BIND_CUSTOM, usage, size));
|
||||
}
|
||||
|
||||
#endif
|
|
@ -611,8 +611,7 @@ int si_pipe_shader_create(
|
|||
if (shader->bo == NULL) {
|
||||
uint32_t *ptr;
|
||||
|
||||
shader->bo = (struct r600_resource*)
|
||||
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, inst_byte_count);
|
||||
shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE, inst_byte_count);
|
||||
if (shader->bo == NULL) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
@ -634,7 +633,7 @@ int si_pipe_shader_create(
|
|||
|
||||
void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
|
||||
{
|
||||
pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
|
||||
si_resource_reference(&shader->bo, NULL);
|
||||
|
||||
memset(&shader->shader,0,sizeof(struct si_shader));
|
||||
}
|
||||
|
|
|
@ -1914,7 +1914,7 @@ static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
|
|||
struct r600_context *rctx = (struct r600_context *)ctx;
|
||||
struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
|
||||
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
|
||||
struct r600_resource *bo;
|
||||
struct si_resource *bo;
|
||||
int i;
|
||||
int has_depth = 0;
|
||||
uint64_t va;
|
||||
|
@ -1925,8 +1925,7 @@ static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
|
|||
|
||||
si_pm4_inval_texture_cache(pm4);
|
||||
|
||||
bo = (struct r600_resource*)
|
||||
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
|
||||
bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
|
||||
count * sizeof(resource[0]->state));
|
||||
ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
|
||||
|
||||
|
@ -1976,7 +1975,7 @@ static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **
|
|||
struct r600_context *rctx = (struct r600_context *)ctx;
|
||||
struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
|
||||
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
|
||||
struct r600_resource *bo;
|
||||
struct si_resource *bo;
|
||||
uint64_t va;
|
||||
char *ptr;
|
||||
int i;
|
||||
|
@ -1986,8 +1985,7 @@ static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **
|
|||
|
||||
si_pm4_inval_texture_cache(pm4);
|
||||
|
||||
bo = (struct r600_resource*)
|
||||
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
|
||||
bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
|
||||
count * sizeof(rstates[0]->val));
|
||||
ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
|
||||
|
||||
|
@ -2025,7 +2023,7 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint i
|
|||
struct pipe_constant_buffer *cb)
|
||||
{
|
||||
struct r600_context *rctx = (struct r600_context *)ctx;
|
||||
struct r600_resource *rbuffer = cb ? r600_resource(cb->buffer) : NULL;
|
||||
struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
|
||||
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
|
||||
uint64_t va_offset;
|
||||
uint32_t offset;
|
||||
|
@ -2068,7 +2066,7 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint i
|
|||
}
|
||||
|
||||
if (cb->buffer != &rbuffer->b.b)
|
||||
pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
|
||||
si_resource_reference(&rbuffer, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -2154,8 +2152,7 @@ si_create_so_target(struct pipe_context *ctx,
|
|||
t->b.buffer_offset = buffer_offset;
|
||||
t->b.buffer_size = buffer_size;
|
||||
|
||||
t->filled_size = (struct r600_resource*)
|
||||
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
|
||||
t->filled_size = si_resource_create_custom(ctx->screen, PIPE_USAGE_STATIC, 4);
|
||||
ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
|
||||
memset(ptr, 0, t->filled_size->buf->size);
|
||||
rctx->ws->buffer_unmap(t->filled_size->cs_buf);
|
||||
|
@ -2168,7 +2165,7 @@ static void si_so_target_destroy(struct pipe_context *ctx,
|
|||
{
|
||||
struct r600_so_target *t = (struct r600_so_target*)target;
|
||||
pipe_resource_reference(&t->b.buffer, NULL);
|
||||
pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
|
||||
si_resource_reference(&t->filled_size, NULL);
|
||||
FREE(t);
|
||||
}
|
||||
|
||||
|
|
|
@ -90,7 +90,7 @@ struct si_shader {
|
|||
struct si_pipe_shader {
|
||||
struct si_shader shader;
|
||||
struct si_pm4_state *pm4;
|
||||
struct r600_resource *bo;
|
||||
struct si_resource *bo;
|
||||
struct si_vertex_element vertex_elements;
|
||||
struct tgsi_token *tokens;
|
||||
unsigned num_sgprs;
|
||||
|
|
|
@ -383,7 +383,7 @@ static void si_update_derived_state(struct r600_context *rctx)
|
|||
static void si_vertex_buffer_update(struct r600_context *rctx)
|
||||
{
|
||||
struct pipe_context *ctx = &rctx->context;
|
||||
struct r600_resource *rbuffer, *t_list_buffer;
|
||||
struct si_resource *rbuffer, *t_list_buffer;
|
||||
struct pipe_vertex_buffer *vertex_buffer;
|
||||
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
|
||||
unsigned i, count, offset;
|
||||
|
@ -396,9 +396,8 @@ static void si_vertex_buffer_update(struct r600_context *rctx)
|
|||
count = rctx->nr_vertex_buffers;
|
||||
assert(count <= 256 / 4);
|
||||
|
||||
t_list_buffer = (struct r600_resource*)
|
||||
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM,
|
||||
PIPE_USAGE_IMMUTABLE, 4 * 4 * count);
|
||||
t_list_buffer = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
|
||||
4 * 4 * count);
|
||||
if (t_list_buffer == NULL) {
|
||||
FREE(pm4);
|
||||
return;
|
||||
|
@ -416,7 +415,7 @@ static void si_vertex_buffer_update(struct r600_context *rctx)
|
|||
|
||||
/* bind vertex buffer once */
|
||||
vertex_buffer = &rctx->vertex_buffer[i];
|
||||
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
|
||||
rbuffer = (struct si_resource*)vertex_buffer->buffer;
|
||||
offset = 0;
|
||||
if (vertex_buffer == NULL || rbuffer == NULL)
|
||||
continue;
|
||||
|
@ -516,7 +515,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
|
|||
rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
|
||||
(R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
|
||||
}
|
||||
rdraw.indices = (struct r600_resource*)ib.buffer;
|
||||
rdraw.indices = (struct si_resource*)ib.buffer;
|
||||
rdraw.indices_bo_offset = ib.offset;
|
||||
rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
|
||||
} else {
|
||||
|
|
Loading…
Reference in New Issue