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pan/midgard: Fix load/store argument sizing 

The swizzles are as-if they were 32-bit regardless of the bitness of the
operation, but the source sizes can and do change depending on the
flags. Account for this in the analysis.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
This commit is contained in:
Alyssa Rosenzweig 2020-02-27 09:36:46 -05:00 committed by Marge Bot
parent ee47ce6ac3
commit fd888d351f
2 changed files with 14 additions and 2 deletions
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5
src/panfrost/midgard/midgard_ra.c
View File

@ -682,16 +682,17 @@ install_registers_instr(
unsigned src2 = ins->src[1];
unsigned src3 = ins->src[2];
midgard_reg_mode m32 = midgard_reg_mode_32;
if (src2 != ~0) {
struct phys_reg src = index_to_reg(ctx, l, src2, mir_srcsize(ins, 1));
struct phys_reg src = index_to_reg(ctx, l, src2, m32);
unsigned component = src.offset / src.size;
assert(component * src.size == src.offset);
ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
}
if (src3 != ~0) {
struct phys_reg src = index_to_reg(ctx, l, src3, mir_srcsize(ins, 2));
struct phys_reg src = index_to_reg(ctx, l, src3, m32);
unsigned component = src.offset / src.size;
assert(component * src.size == src.offset);
ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);

11
src/panfrost/midgard/mir.c
View File

@ -255,6 +255,17 @@ mir_typesize(midgard_instruction *ins)
midgard_reg_mode
mir_srcsize(midgard_instruction *ins, unsigned i)
{
if (ins->type == TAG_LOAD_STORE_4) {
if (OP_HAS_ADDRESS(ins->load_store.op)) {
if (i == 1)
return midgard_reg_mode_64;
else if (i == 2) {
bool zext = ins->load_store.arg_1 & 0x80;
return zext ? midgard_reg_mode_32 : midgard_reg_mode_64;
}
}
}
/* TODO: 16-bit textures/ldst */
if (ins->type == TAG_TEXTURE_4 || ins->type == TAG_LOAD_STORE_4)
return midgard_reg_mode_32;