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freedreno: Add FD_DBG() macro 

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9264>
This commit is contained in:
Rob Clark 2021-02-24 13:31:43 -08:00 committed by Marge Bot
parent 5d217774f2
commit fd4d759622
22 changed files with 43 additions and 42 deletions
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2
src/gallium/drivers/freedreno/a2xx/fd2_emit.c
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@ -426,7 +426,7 @@ fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
/* enable perfcntrs */
OUT_PKT0(ring, REG_A2XX_CP_PERFMON_CNTL, 1);
OUT_RING(ring, COND(fd_mesa_debug & FD_DBG_PERFC, 1));
OUT_RING(ring, COND(FD_DBG(PERFC), 1));
/* note: perfcntrs don't work without the PM_OVERRIDE bit */
OUT_PKT0(ring, REG_A2XX_RBBM_PM_OVERRIDE1, 2);

2
src/gallium/drivers/freedreno/a2xx/fd2_screen.c
View File

@ -109,7 +109,7 @@ fd2_screen_init(struct pipe_screen *pscreen)
pscreen->is_format_supported = fd2_screen_is_format_supported;
screen->setup_slices = fd2_setup_slices;
if (fd_mesa_debug & FD_DBG_TTILE)
if (FD_DBG(TTILE))
screen->tile_mode = fd2_tile_mode;
fd2_emit_init_screen(pscreen);

2
src/gallium/drivers/freedreno/a2xx/ir2_assemble.c
View File

@ -541,7 +541,7 @@ void assemble(struct ir2_context *ctx, bool binning)
for (int i = 0; i < ctx->info->num_fetch_instrs; i++)
ctx->info->fetch_info[i].offset += cfdwords;
if (fd_mesa_debug & FD_DBG_DISASM) {
if (FD_DBG(DISASM)) {
DBG("disassemble: type=%d", ctx->so->type);
disasm_a2xx(dwords, sizedwords, 0, ctx->so->type);
}

4
src/gallium/drivers/freedreno/a2xx/ir2_nir.c
View File

@ -109,7 +109,7 @@ ir2_optimize_nir(nir_shader *s, bool lower)
.lower_rect = 0,
};
if (fd_mesa_debug & FD_DBG_DISASM) {
if (FD_DBG(DISASM)) {
debug_printf("----------------------\n");
nir_print_shader(s, stdout);
debug_printf("----------------------\n");
@ -1119,7 +1119,7 @@ ir2_nir_compile(struct ir2_context *ctx, bool binning)
nir_sweep(ctx->nir);
if (fd_mesa_debug & FD_DBG_DISASM) {
if (FD_DBG(DISASM)) {
debug_printf("----------------------\n");
nir_print_shader(ctx->nir, stdout);
debug_printf("----------------------\n");

2
src/gallium/drivers/freedreno/a3xx/fd3_program.c
View File

@ -66,7 +66,7 @@ emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
sb = SB_FRAG_SHADER;
}
if (fd_mesa_debug & FD_DBG_DIRECT) {
if (FD_DBG(DIRECT)) {
sz = si->sizedwords;
src = SS_DIRECT;
bin = fd_bo_map(so->bo);

2
src/gallium/drivers/freedreno/a3xx/fd3_screen.c
View File

@ -111,6 +111,6 @@ fd3_screen_init(struct pipe_screen *pscreen)
ir3_screen_init(pscreen);
screen->setup_slices = fd3_setup_slices;
if (fd_mesa_debug & FD_DBG_TTILE)
if (FD_DBG(TTILE))
screen->tile_mode = fd3_tile_mode;
}

2
src/gallium/drivers/freedreno/a4xx/fd4_program.c
View File

@ -45,7 +45,7 @@ emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
enum a4xx_state_src src;
uint32_t i, sz, *bin;
if (fd_mesa_debug & FD_DBG_DIRECT) {
if (FD_DBG(DIRECT)) {
sz = si->sizedwords;
src = SS4_DIRECT;
bin = fd_bo_map(so->bo);

2
src/gallium/drivers/freedreno/a5xx/fd5_context.c
View File

@ -98,7 +98,7 @@ fd5_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
fd5_prog_init(pctx);
fd5_emit_init(pctx);
if (!(fd_mesa_debug & FD_DBG_NOBLIT))
if (!FD_DBG(NOBLIT))
fd5_ctx->base.blit = fd5_blitter_blit;
pctx = fd_context_init(&fd5_ctx->base, pscreen, primtypes, priv, flags);

2
src/gallium/drivers/freedreno/a5xx/fd5_program.c
View File

@ -48,7 +48,7 @@ fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
enum a4xx_state_src src;
uint32_t i, sz, *bin;
if (fd_mesa_debug & FD_DBG_DIRECT) {
if (FD_DBG(DIRECT)) {
sz = si->sizedwords;
src = SS4_DIRECT;
bin = fd_bo_map(so->bo);

2
src/gallium/drivers/freedreno/a5xx/fd5_resource.c
View File

@ -59,7 +59,7 @@ fd5_setup_slices(struct fd_resource *rsc)
{
struct pipe_resource *prsc = &rsc->base;
if ((fd_mesa_debug & FD_DBG_LRZ) && has_depth(rsc->base.format))
if (FD_DBG(LRZ) && has_depth(rsc->base.format))
setup_lrz(rsc);
fdl5_layout(&rsc->layout, prsc->format, fd_resource_nr_samples(prsc),

2
src/gallium/drivers/freedreno/a5xx/fd5_screen.c
View File

@ -130,7 +130,7 @@ fd5_screen_init(struct pipe_screen *pscreen)
pscreen->is_format_supported = fd5_screen_is_format_supported;
screen->setup_slices = fd5_setup_slices;
if (fd_mesa_debug & FD_DBG_TTILE)
if (FD_DBG(TTILE))
screen->tile_mode = fd5_tile_mode;
fd5_emit_init_screen(pscreen);

2
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View File

@ -1096,7 +1096,7 @@ fd6_blitter_init(struct pipe_context *pctx)
{
fd_context(pctx)->clear_ubwc = fd6_clear_ubwc;
if (fd_mesa_debug & FD_DBG_NOBLIT)
if (FD_DBG(NOBLIT))
return;
fd_context(pctx)->blit = fd6_blit;

2
src/gallium/drivers/freedreno/a6xx/fd6_resource.c
View File

@ -159,7 +159,7 @@ fd6_setup_slices(struct fd_resource *rsc)
{
struct pipe_resource *prsc = &rsc->base;
if (!(fd_mesa_debug & FD_DBG_NOLRZ) && has_depth(rsc->base.format))
if (!FD_DBG(NOLRZ) && has_depth(rsc->base.format))
setup_lrz(rsc);
if (rsc->layout.ubwc && !ok_ubwc_format(rsc->base.screen, rsc->base.format))

4
src/gallium/drivers/freedreno/freedreno_batch.c
View File

@ -49,7 +49,7 @@ alloc_ring(struct fd_batch *batch, unsigned sz, enum fd_ringbuffer_flags flags)
* size of zero.
*/
if ((fd_device_version(ctx->screen->dev) >= FD_VERSION_UNLIMITED_CMDS) &&
!(fd_mesa_debug & FD_DBG_NOGROW)){
!FD_DBG(NOGROW)) {
flags |= FD_RINGBUFFER_GROWABLE;
sz = 0;
}
@ -536,7 +536,7 @@ fd_batch_check_size(struct fd_batch *batch)
{
debug_assert(!batch->flushed);
if (unlikely(fd_mesa_debug & FD_DBG_FLUSH)) {
if (FD_DBG(FLUSH)) {
fd_batch_flush(batch);
return;
}

2
src/gallium/drivers/freedreno/freedreno_batch.h
View File

@ -37,7 +37,7 @@
#include "freedreno_util.h"
#ifdef DEBUG
# define BATCH_DEBUG (fd_mesa_debug & FD_DBG_MSGS)
# define BATCH_DEBUG FD_DBG(MSGS)
#else
# define BATCH_DEBUG 0
#endif

6
src/gallium/drivers/freedreno/freedreno_context.c
View File

@ -339,8 +339,8 @@ fd_context_destroy(struct pipe_context *pctx)
u_trace_context_fini(&ctx->trace_context);
if (fd_mesa_debug & (FD_DBG_BSTAT | FD_DBG_MSGS)) {
printf("batch_total=%u, batch_sysmem=%u, batch_gmem=%u, batch_nondraw=%u, batch_restore=%u\n",
if (FD_DBG(BSTAT) || FD_DBG(MSGS)) {
mesa_logi("batch_total=%u, batch_sysmem=%u, batch_gmem=%u, batch_nondraw=%u, batch_restore=%u\n",
(uint32_t)ctx->stats.batch_total, (uint32_t)ctx->stats.batch_sysmem,
(uint32_t)ctx->stats.batch_gmem, (uint32_t)ctx->stats.batch_nondraw,
(uint32_t)ctx->stats.batch_restore);
@ -527,7 +527,7 @@ fd_context_init(struct fd_context *ctx, struct pipe_screen *pscreen,
int i;
/* lower numerical value == higher priority: */
if (fd_mesa_debug & FD_DBG_HIPRIO)
if (FD_DBG(HIPRIO))
prio = 0;
else if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
prio = 0;

6
src/gallium/drivers/freedreno/freedreno_draw.c
View File

@ -259,7 +259,7 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
* to be able to emulate it, to determine if game is feeding us
* bogus data:
*/
if (indirect && indirect->buffer && (fd_mesa_debug & FD_DBG_NOINDR)) {
if (indirect && indirect->buffer && FD_DBG(NOINDR)) {
util_draw_indirect(pctx, info, indirect);
return;
}
@ -368,7 +368,7 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
for (unsigned i = 0; i < ctx->streamout.num_targets; i++)
ctx->streamout.offsets[i] += draws[0].count;
if (fd_mesa_debug & FD_DBG_DDRAW)
if (FD_DBG(DDRAW))
fd_context_all_dirty(ctx);
fd_batch_unlock_submit(batch);
@ -483,7 +483,7 @@ fd_clear(struct pipe_context *pctx, unsigned buffers,
fd_batch_update_queries(batch);
if (ctx->clear(ctx, buffers, color, depth, stencil)) {
if (fd_mesa_debug & FD_DBG_DCLEAR)
if (FD_DBG(DCLEAR))
fd_context_all_dirty(ctx);
fallback = false;

10
src/gallium/drivers/freedreno/freedreno_gmem.c
View File

@ -225,7 +225,7 @@ calc_nbins(struct gmem_key *key, struct fd_gmem_stateobj *gmem)
uint32_t max_width = screen->info.tile_max_w;
uint32_t max_height = screen->info.tile_max_h;
if (fd_mesa_debug & FD_DBG_MSGS) {
if (FD_DBG(MSGS)) {
debug_printf("binning input: cbuf cpp:");
for (unsigned i = 0; i < key->nr_cbufs; i++)
debug_printf(" %d", key->cbuf_cpp[i]);
@ -493,7 +493,7 @@ gmem_key_init(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
} else {
struct pipe_scissor_state *scissor = &batch->max_scissor;
if (fd_mesa_debug & FD_DBG_NOSCIS) {
if (FD_DBG(NOSCIS)) {
scissor->minx = 0;
scissor->miny = 0;
scissor->maxx = pfb->width;
@ -656,7 +656,7 @@ flush_ring(struct fd_batch *batch)
uint32_t timestamp;
int out_fence_fd = -1;
if (unlikely(fd_mesa_debug & FD_DBG_NOHW))
if (FD_DBG(NOHW))
return;
fd_submit_flush(batch->submit, batch->in_fence_fd,
@ -683,7 +683,7 @@ fd_gmem_render_tiles(struct fd_batch *batch)
if (batch->cleared || batch->gmem_reason ||
((batch->num_draws > 5) && !batch->blit) ||
(pfb->samples > 1)) {
} else if (!(fd_mesa_debug & FD_DBG_NOBYPASS)) {
} else if (!FD_DBG(NOBYPASS)) {
sysmem = true;
}
@ -693,7 +693,7 @@ fd_gmem_render_tiles(struct fd_batch *batch)
}
}
if (fd_mesa_debug & FD_DBG_NOGMEM)
if (FD_DBG(NOGMEM))
sysmem = true;
/* Layered rendering always needs bypass. */

6
src/gallium/drivers/freedreno/freedreno_resource.c
View File

@ -984,7 +984,7 @@ fd_resource_allocate_and_resolve(struct pipe_screen *pscreen,
linear = true;
}
if (fd_mesa_debug & FD_DBG_NOTILE)
if (FD_DBG(NOTILE))
linear = true;
/* Normally, for non-shared buffers, allow buffer compression if
@ -1012,7 +1012,7 @@ fd_resource_allocate_and_resolve(struct pipe_screen *pscreen,
}
}
allow_ubwc &= !(fd_mesa_debug & FD_DBG_NOUBWC);
allow_ubwc &= !FD_DBG(NOUBWC);
pipe_reference_init(&prsc->reference, 1);
@ -1056,7 +1056,7 @@ fd_resource_allocate_and_resolve(struct pipe_screen *pscreen,
size = rsc->layout.layer_size * prsc->array_size;
}
if (fd_mesa_debug & FD_DBG_LAYOUT)
if (FD_DBG(LAYOUT))
fdl_dump_layout(&rsc->layout);
/* Hand out the resolved size. */

10
src/gallium/drivers/freedreno/freedreno_screen.c
View File

@ -498,7 +498,7 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
*
* See: https://code.google.com/p/android/issues/detail?id=206513
*/
if (fd_mesa_debug & FD_DBG_DEQP)
if (FD_DBG(DEQP))
return 48.0f;
return 127.0f;
case PIPE_CAPF_MAX_POINT_WIDTH:
@ -610,7 +610,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
return ((is_a5xx(screen) || is_a6xx(screen)) &&
(shader == PIPE_SHADER_COMPUTE ||
shader == PIPE_SHADER_FRAGMENT) &&
!(fd_mesa_debug & FD_DBG_NOFP16));
!FD_DBG(NOFP16));
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
@ -894,7 +894,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
fd_mesa_debug = debug_get_option_fd_mesa_debug();
if (fd_mesa_debug & FD_DBG_NOBIN)
if (FD_DBG(NOBIN))
fd_binning_enabled = false;
if (!screen)
@ -1035,7 +1035,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
freedreno_dev_info_init(&screen->info, screen->gpu_id);
if (fd_mesa_debug & FD_DBG_PERFC) {
if (FD_DBG(PERFC)) {
screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
&screen->num_perfcntr_groups);
}
@ -1045,7 +1045,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
* buffers would be too much otherwise.
*/
if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
screen->reorder = !FD_DBG(INORDER);
if (BATCH_DEBUG)
screen->live_batches = _mesa_pointer_set_create(NULL);

6
src/gallium/drivers/freedreno/freedreno_util.h
View File

@ -96,8 +96,10 @@ enum fd_debug_flag {
extern int fd_mesa_debug;
extern bool fd_binning_enabled;
#define FD_DBG(category) unlikely(fd_mesa_debug & FD_DBG_##category)
#define DBG(fmt, ...) \
do { if (fd_mesa_debug & FD_DBG_MSGS) \
do { if (FD_DBG(MSGS)) \
mesa_logd("%s:%d: "fmt, \
__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
@ -107,7 +109,7 @@ extern bool fd_binning_enabled;
} while(0)
#define perf_debug(...) do { \
if (unlikely(fd_mesa_debug & FD_DBG_PERF)) \
if (FD_DBG(PERF)) \
mesa_logw(__VA_ARGS__); \
} while(0)

7
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
View File

@ -67,15 +67,14 @@ struct ir3_shader_state {
static bool
initial_variants_synchronous(struct fd_context *ctx)
{
return unlikely(ctx->debug.debug_message ||
(fd_mesa_debug & FD_DBG_SHADERDB)) ||
(fd_mesa_debug & FD_DBG_SERIALC);
return unlikely(ctx->debug.debug_message) ||
FD_DBG(SHADERDB) || FD_DBG(SERIALC);
}
static void
dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
{
if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
if (!FD_DBG(SHADERDB))
return;
pipe_debug_message(debug, SHADER_INFO,