intel/compiler: Don't have sepearate, per-Gen nir_options
Instead, just have separate scalar vs. vector nir_options and do per-Gen "fix ups". Suggested-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -69,12 +69,6 @@ static const struct nir_shader_compiler_options scalar_nir_options = {
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COMMON_SCALAR_OPTIONS,
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COMMON_SCALAR_OPTIONS,
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};
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};
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static const struct nir_shader_compiler_options scalar_nir_options_gen11 = {
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COMMON_OPTIONS,
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COMMON_SCALAR_OPTIONS,
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.lower_flrp32 = true,
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};
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static const struct nir_shader_compiler_options vector_nir_options = {
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static const struct nir_shader_compiler_options vector_nir_options = {
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COMMON_OPTIONS,
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COMMON_OPTIONS,
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@ -84,27 +78,6 @@ static const struct nir_shader_compiler_options vector_nir_options = {
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*/
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*/
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.fdot_replicates = true,
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.fdot_replicates = true,
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/* Prior to Gen6, there are no three source operations for SIMD4x2. */
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.lower_flrp32 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.max_unroll_iterations = 32,
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};
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static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
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COMMON_OPTIONS,
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/* In the vec4 backend, our dpN instruction replicates its result to all the
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* components of a vec4. We would like NIR to give us replicated fdot
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* instructions because it can optimize better for us.
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*/
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.fdot_replicates = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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@ -197,11 +170,18 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
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struct nir_shader_compiler_options *nir_options =
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struct nir_shader_compiler_options *nir_options =
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rzalloc(compiler, struct nir_shader_compiler_options);
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rzalloc(compiler, struct nir_shader_compiler_options);
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if (is_scalar) {
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if (is_scalar) {
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*nir_options =
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*nir_options = scalar_nir_options;
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devinfo->gen < 11 ? scalar_nir_options : scalar_nir_options_gen11;
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if (devinfo->gen >= 11) {
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nir_options->lower_flrp32 = true;
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}
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} else {
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} else {
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*nir_options =
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*nir_options = vector_nir_options;
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devinfo->gen < 6 ? vector_nir_options : vector_nir_options_gen6;
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if (devinfo->gen < 6) {
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/* Prior to Gen6, there are no three source operations. */
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nir_options->lower_flrp32 = true;
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}
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}
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}
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nir_options->lower_int64_options = int64_options;
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nir_options->lower_int64_options = int64_options;
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nir_options->lower_doubles_options = fp64_options;
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nir_options->lower_doubles_options = fp64_options;
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