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i965/fs: fix 32-bit data type to int64 conversion on BSW/BXT 

The 32-bit to 64-bit conversions need to have the 32-bit
data source elements aligned to 64-bit but only with doubles as
destination type.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Samuel Iglesias Gonsálvez 2017-02-10 14:06:43 +01:00
parent 172c48cc15
commit fccbad73ef
1 changed files with 7 additions and 7 deletions
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14
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
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@ -655,13 +655,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_f2d:
case nir_op_i2d:
case nir_op_u2d:
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_i2i64:
case nir_op_i2u64:
case nir_op_u2i64:
case nir_op_u2u64:
case nir_op_b2i64:
/* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
*
* "When source or destination is 64b (...), regioning in Align1
@ -686,6 +679,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
break;
}
/* fallthrough */
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_i2i64:
case nir_op_i2u64:
case nir_op_u2i64:
case nir_op_u2u64:
case nir_op_b2i64:
case nir_op_d2f:
case nir_op_d2i:
case nir_op_d2u: