spirv: Flip the tessellation winding order
It's not SPIR-V that's backwards from GLSL, it's Vulkan that's backwards from GL. Let's make NIR consistent with the source language and do the flipping inside the Vulkan driver instead. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -262,6 +262,7 @@ radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
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if (tcs_nir == NULL)
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return;
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tes_nir->info.tess.ccw = !tes_nir->info.tess.ccw;
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nir_lower_tes_patch_vertices(tes_nir,
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tcs_nir->info.tess.tcs_vertices_out);
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@ -2951,17 +2951,12 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct vtn_value *entry_point,
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case SpvExecutionModeVertexOrderCw:
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assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
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b->shader->stage == MESA_SHADER_TESS_EVAL);
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/* Vulkan's notion of CCW seems to match the hardware backends,
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* but be the opposite of OpenGL. Currently NIR follows GL semantics,
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* so we set it backwards here.
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*/
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b->shader->info.tess.ccw = true;
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b->shader->info.tess.ccw = false;
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break;
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case SpvExecutionModeVertexOrderCcw:
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assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
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b->shader->stage == MESA_SHADER_TESS_EVAL);
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/* Backwards; see above */
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b->shader->info.tess.ccw = false;
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b->shader->info.tess.ccw = true;
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break;
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case SpvExecutionModePointMode:
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assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
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@ -1217,7 +1217,18 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) {
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te.Partitioning = tes_prog_data->partitioning;
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te.OutputTopology = tes_prog_data->output_topology;
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/* Vulkan has its winding order backwards from GL so TRI_CCW becomes
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* TRI_CW and vice versa.
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*/
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if (tes_prog_data->output_topology == OUTPUT_TRI_CCW) {
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te.OutputTopology = OUTPUT_TRI_CW;
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} else if (tes_prog_data->output_topology == OUTPUT_TRI_CW) {
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te.OutputTopology = OUTPUT_TRI_CCW;
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} else {
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te.OutputTopology = tes_prog_data->output_topology;
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}
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te.TEDomain = tes_prog_data->domain;
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te.TEEnable = true;
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te.MaximumTessellationFactorOdd = 63.0;
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