pan/midgard: Support loads from R11G11B10 in a blend shader
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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3af5a398f3
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@ -51,11 +51,16 @@ static nir_intrinsic_op
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nir_best_load_for_format(
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const struct util_format_description *desc,
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unsigned *special_bitsize,
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unsigned *special_components,
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unsigned gpu_id)
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{
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if (util_format_is_unorm8(desc) && gpu_id != 0x750) {
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*special_bitsize = 16;
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return nir_intrinsic_load_output_u8_as_fp16_pan;
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} else if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) {
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*special_bitsize = 32;
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*special_components = 1;
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return nir_intrinsic_load_raw_output_pan;
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} else
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return nir_intrinsic_load_raw_output_pan;
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}
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@ -244,7 +249,24 @@ nir_native_to_shader(nir_builder *b,
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return nir_unorm8_to_float(b, c_native);
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else if (homogenous_bits && float_or_pure_int)
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return c_native; /* type is already correct */
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else {
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/* Special formats */
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switch (desc->format) {
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case PIPE_FORMAT_R11G11B10_FLOAT: {
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nir_ssa_def *unpacked = nir_format_unpack_11f11f10f(b, c_native);
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/* Extend to vec4 with alpha */
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nir_ssa_def *components[4] = {
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nir_channel(b, unpacked, 0),
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nir_channel(b, unpacked, 1),
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nir_channel(b, unpacked, 2),
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nir_imm_float(b, 1.0)
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};
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return nir_vec(b, components, 4);
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}
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default:
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printf("%s\n", desc->name);
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unreachable("Unknown format name");
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}
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@ -345,15 +367,17 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format format,
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/* Determine the best op for the format/hardware */
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unsigned bitsize = raw_bitsize_in;
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unsigned components = 4;
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nir_intrinsic_op op = nir_best_load_for_format(format_desc,
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&bitsize,
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&components,
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gpu_id);
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/* Rewrite to use a native load by creating a new intrinsic */
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nir_intrinsic_instr *new = nir_intrinsic_instr_create(shader, op);
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new->num_components = 4;
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new->num_components = components;
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nir_ssa_dest_init(&new->instr, &new->dest, 4, bitsize, NULL);
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nir_ssa_dest_init(&new->instr, &new->dest, components, bitsize, NULL);
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nir_builder_instr_insert(&b, &new->instr);
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/* Convert the raw value */
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