r600g: move invariant register updates into start_cs for r6xx-r7xx
This commit is contained in:
Marek Olšák
parent
e2809849ec
commit
fbebd431ec
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@ -255,8 +255,6 @@ static const struct r600_reg r600_ctl_const_list[] = {
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static const struct r600_reg r600_context_reg_list[] = {
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{R_028A4C_PA_SC_MODE_CNTL, 0, 0},
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{R_028028_DB_STENCIL_CLEAR, 0, 0},
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{R_02802C_DB_DEPTH_CLEAR, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -267,7 +265,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
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{R_028100_CB_COLOR0_MASK, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -278,7 +275,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
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{R_028104_CB_COLOR1_MASK, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -289,7 +285,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
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{R_028108_CB_COLOR2_MASK, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -300,7 +295,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
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{R_02810C_CB_COLOR3_MASK, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -311,7 +305,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
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{R_028110_CB_COLOR4_MASK, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -322,7 +315,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
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{R_028114_CB_COLOR5_MASK, 0, 0},
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{R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
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{R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
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{R_028078_CB_COLOR6_SIZE, 0, 0},
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@ -331,7 +323,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
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{R_028118_CB_COLOR6_MASK, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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@ -340,7 +331,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_02809C_CB_COLOR7_VIEW, 0, 0},
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{R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
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{R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
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{R_02811C_CB_COLOR7_MASK, 0, 0},
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{R_028120_CB_CLEAR_RED, 0, 0},
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{R_028124_CB_CLEAR_GREEN, 0, 0},
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{R_028128_CB_CLEAR_BLUE, 0, 0},
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@ -366,9 +356,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_028430_DB_STENCILREFMASK, 0, 0},
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{R_028434_DB_STENCILREFMASK_BF, 0, 0},
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{R_028438_SX_ALPHA_REF, 0, 0},
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{R_0286DC_SPI_FOG_CNTL, 0, 0},
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{R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0},
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{R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0},
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{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
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{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
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{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
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@ -382,27 +369,15 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_028804_CB_BLEND_CONTROL, 0, 0},
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{R_028808_CB_COLOR_CONTROL, 0, 0},
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{R_02880C_DB_SHADER_CONTROL, 0, 0},
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{R_028C04_PA_SC_AA_CONFIG, 0, 0},
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{R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
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{R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
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{R_028C30_CB_CLRCMP_CONTROL, 0, 0},
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{R_028C34_CB_CLRCMP_SRC, 0, 0},
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{R_028C38_CB_CLRCMP_DST, 0, 0},
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{R_028C3C_CB_CLRCMP_MSK, 0, 0},
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{R_028C48_PA_SC_AA_MASK, 0, 0},
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{R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0},
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{R_028D44_DB_ALPHA_TO_MASK, 0, 0},
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{R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
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{R_028000_DB_DEPTH_SIZE, 0, 0},
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{R_028004_DB_DEPTH_VIEW, 0, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
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{R_028D24_DB_HTILE_SURFACE, 0, 0},
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{R_028D30_DB_PRELOAD_CONTROL, 0, 0},
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{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
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{R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
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{R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
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{R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
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{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
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{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
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{R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
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@ -414,13 +389,10 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
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{R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
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{R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
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{R_028230_PA_SC_EDGERULE, 0, 0},
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{R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
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{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
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{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
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{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
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{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
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{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
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{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
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{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
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{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
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@ -430,20 +402,12 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
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{R_028810_PA_CL_CLIP_CNTL, 0, 0},
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{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
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{R_028818_PA_CL_VTE_CNTL, 0, 0},
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{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
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{R_028820_PA_CL_NANINF_CNTL, 0, 0},
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{R_028A00_PA_SU_POINT_SIZE, 0, 0},
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{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
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{R_028A08_PA_SU_LINE_CNTL, 0, 0},
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{R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
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{R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0},
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{R_028C00_PA_SC_LINE_CNTL, 0, 0},
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{R_028C08_PA_SU_VTX_CNTL, 0, 0},
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{R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
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{R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
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{R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
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{R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
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{R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
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{R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
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{R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
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@ -525,7 +489,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
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{R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0},
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{R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
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{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
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{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
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@ -567,7 +530,6 @@ static const struct r600_reg r600_context_reg_list[] = {
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{GROUP_FORCE_NEW_BLOCK, 0, 0},
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{R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
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{R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
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{R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0},
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{R_028408_VGT_INDX_OFFSET, 0, 0},
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{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
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{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
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@ -502,10 +502,12 @@ unsigned r600_tex_compare(unsigned compare);
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#define PKT3_SET_CONFIG_REG 0x68
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#define PKT3_SET_CONTEXT_REG 0x69
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#define PKT3_SET_CTL_CONST 0x6F
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#define PKT3_SET_LOOP_CONST 0x6C
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#define R600_CONFIG_REG_OFFSET 0x08000
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#define R600_CONTEXT_REG_OFFSET 0x28000
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#define R600_CTL_CONST_OFFSET 0x3CFF0
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#define R600_LOOP_CONST_OFFSET 0X0003E200
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#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
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#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
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@ -542,6 +544,14 @@ static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsi
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cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
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}
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static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
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{
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assert(reg >= R600_LOOP_CONST_OFFSET);
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assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
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cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
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cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
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}
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static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
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{
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r600_store_config_reg_seq(cb, reg, 1);
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@ -560,6 +570,12 @@ static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned
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r600_store_value(cb, value);
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}
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static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
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{
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r600_store_loop_const_seq(cb, reg, 1);
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r600_store_value(cb, value);
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}
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void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
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void r600_release_command_buffer(struct r600_command_buffer *cb);
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@ -762,17 +762,8 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
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}
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dsa->alpha_ref = alpha_ref;
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r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
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return rstate;
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}
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@ -831,7 +822,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
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}
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r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
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/* point size 12.4 fixed point */
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tmp = (unsigned)(state->point_size * 8.0);
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r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
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@ -861,17 +851,11 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
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r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
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NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
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S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
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NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
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r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
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@ -1327,15 +1311,12 @@ static void r600_set_viewport_state(struct pipe_context *ctx,
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rctx->viewport = *state;
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rstate->id = R600_PIPE_STATE_VIEWPORT;
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r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
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r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
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r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
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r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
|
||||
|
||||
free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
|
||||
rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
|
||||
|
|
@ -1517,9 +1498,6 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
|
|||
r600_pipe_state_add_reg(rstate,
|
||||
R_0280C0_CB_COLOR0_TILE + cb * 4,
|
||||
0, &rtex->resource, RADEON_USAGE_READWRITE);
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_028100_CB_COLOR0_MASK + cb * 4,
|
||||
0x00000000, NULL, 0);
|
||||
}
|
||||
|
||||
static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
|
||||
|
|
@ -1652,35 +1630,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
|
|||
r600_pipe_state_add_reg(rstate,
|
||||
R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
|
||||
NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
|
||||
NULL, 0);
|
||||
if (rctx->chip_class >= R700) {
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
|
||||
NULL, 0);
|
||||
}
|
||||
|
||||
r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
|
||||
shader_control, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
|
||||
shader_mask, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
|
||||
0x01000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
|
||||
0x000000FF, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
|
||||
0xFFFFFFFF, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
|
||||
0xFFFFFFFF, NULL, 0);
|
||||
|
||||
free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
|
||||
rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
|
||||
|
|
@ -1827,6 +1781,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
|
|||
enum radeon_family family;
|
||||
struct r600_command_buffer *cb = &rctx->atom_start_cs;
|
||||
uint32_t tmp;
|
||||
unsigned i;
|
||||
|
||||
r600_init_command_buffer(cb, 256, EMIT_EARLY);
|
||||
|
||||
|
|
@ -2064,6 +2019,71 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
|
|||
r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
|
||||
|
||||
r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
|
||||
|
||||
r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
|
||||
r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
|
||||
r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
|
||||
|
||||
r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
|
||||
r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
|
||||
r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
|
||||
r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
|
||||
|
||||
r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
|
||||
r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
|
||||
r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
|
||||
|
||||
r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
|
||||
|
||||
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
|
||||
r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
|
||||
|
||||
r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
|
||||
r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
|
||||
r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
|
||||
|
||||
r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
|
||||
r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
|
||||
r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
|
||||
r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
|
||||
r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
|
||||
r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
|
||||
r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
|
||||
|
||||
r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
|
||||
r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
|
||||
r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
|
||||
|
||||
r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
|
||||
|
||||
r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
|
||||
for (i = 0; i < 8; i++) {
|
||||
r600_store_value(cb, 0);
|
||||
}
|
||||
|
||||
r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
|
||||
|
||||
if (rctx->chip_class >= R700) {
|
||||
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
|
||||
}
|
||||
|
||||
r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
|
||||
r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
|
||||
r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
|
||||
r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
|
||||
r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
|
||||
|
||||
r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
|
||||
|
||||
r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
|
||||
r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
|
||||
r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
|
||||
|
||||
r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
|
||||
r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
|
||||
|
||||
r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
|
||||
r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
|
||||
}
|
||||
|
||||
void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
|
||||
|
|
@ -2174,18 +2194,11 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad
|
|||
r600_pipe_state_add_reg(rstate,
|
||||
R_028854_SQ_PGM_EXPORTS_PS,
|
||||
exports_ps, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_0288CC_SQ_PGM_CF_OFFSET_PS,
|
||||
0x00000000, NULL, 0);
|
||||
/* only set some bits here, the other bits are set in the dsa state */
|
||||
r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
|
||||
db_shader_control,
|
||||
NULL, 0);
|
||||
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
|
||||
NULL, 0);
|
||||
|
||||
shader->sprite_coord_enable = rctx->sprite_coord_enable;
|
||||
if (rctx->rasterizer)
|
||||
shader->flatshade = rctx->rasterizer->flatshade;
|
||||
|
|
@ -2232,17 +2245,10 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad
|
|||
S_028868_NUM_GPRS(rshader->bc.ngpr) |
|
||||
S_028868_STACK_SIZE(rshader->bc.nstack),
|
||||
NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_0288D0_SQ_PGM_CF_OFFSET_VS,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_028858_SQ_PGM_START_VS,
|
||||
0, shader->bo, RADEON_USAGE_READ);
|
||||
|
||||
r600_pipe_state_add_reg(rstate,
|
||||
R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
|
||||
NULL, 0);
|
||||
|
||||
shader->pa_cl_vs_out_cntl =
|
||||
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
|
||||
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
|
||||
|
|
@ -2259,10 +2265,6 @@ void r600_fetch_shader(struct pipe_context *ctx,
|
|||
rstate = &ve->rstate;
|
||||
rstate->id = R600_PIPE_STATE_FETCH_SHADER;
|
||||
rstate->nregs = 0;
|
||||
r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
|
||||
0x00000000, NULL, 0);
|
||||
r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
|
||||
0,
|
||||
ve->fetch_shader, RADEON_USAGE_READ);
|
||||
|
|
|
|||
Loading…
Reference in New Issue