r600g: move some queries into winsys/radeon
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
ce12f82692
commit
fb8cf51eeb
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@ -76,12 +76,12 @@ struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon)
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unsigned r600_get_clock_crystal_freq(struct radeon *radeon)
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{
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return radeon->clock_crystal_freq;
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return radeon->info.r600_clock_crystal_freq;
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}
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unsigned r600_get_num_backends(struct radeon *radeon)
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{
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return radeon->num_backends;
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return radeon->info.r600_num_backends;
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}
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unsigned r600_get_num_tile_pipes(struct radeon *radeon)
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@ -96,7 +96,7 @@ unsigned r600_get_backend_map(struct radeon *radeon)
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unsigned r600_get_minor_version(struct radeon *radeon)
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{
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return radeon->minor_version;
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return radeon->info.drm_minor;
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}
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static int r600_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
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@ -191,59 +191,16 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
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static int radeon_drm_get_tiling(struct radeon *radeon)
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{
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struct drm_radeon_info info = {};
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int r;
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uint32_t tiling_config = 0;
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uint32_t tiling_config = radeon->info.r600_tiling_config;
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info.request = RADEON_INFO_TILING_CONFIG;
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info.value = (uintptr_t)&tiling_config;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
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sizeof(struct drm_radeon_info));
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if (r)
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if (!tiling_config)
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return 0;
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if (radeon->chip_class == R600 || radeon->chip_class == R700) {
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r = r600_interpret_tiling(radeon, tiling_config);
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return r600_interpret_tiling(radeon, tiling_config);
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} else {
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r = eg_interpret_tiling(radeon, tiling_config);
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return eg_interpret_tiling(radeon, tiling_config);
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}
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return r;
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}
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static int radeon_get_clock_crystal_freq(struct radeon *radeon)
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{
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struct drm_radeon_info info = {};
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uint32_t clock_crystal_freq = 0;
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int r;
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info.request = RADEON_INFO_CLOCK_CRYSTAL_FREQ;
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info.value = (uintptr_t)&clock_crystal_freq;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
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sizeof(struct drm_radeon_info));
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if (r)
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return r;
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radeon->clock_crystal_freq = clock_crystal_freq;
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return 0;
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}
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static int radeon_get_num_backends(struct radeon *radeon)
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{
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struct drm_radeon_info info = {};
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uint32_t num_backends = 0;
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int r;
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info.request = RADEON_INFO_NUM_BACKENDS;
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info.value = (uintptr_t)&num_backends;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
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sizeof(struct drm_radeon_info));
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if (r)
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return r;
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radeon->num_backends = num_backends;
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return 0;
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}
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static int radeon_get_num_tile_pipes(struct radeon *radeon)
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@ -254,7 +211,7 @@ static int radeon_get_num_tile_pipes(struct radeon *radeon)
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info.request = RADEON_INFO_NUM_TILE_PIPES;
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info.value = (uintptr_t)&num_tile_pipes;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
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r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_INFO, &info,
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sizeof(struct drm_radeon_info));
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if (r)
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return r;
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@ -271,7 +228,7 @@ static int radeon_get_backend_map(struct radeon *radeon)
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info.request = RADEON_INFO_BACKEND_MAP;
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info.value = (uintptr_t)&backend_map;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
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r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_INFO, &info,
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sizeof(struct drm_radeon_info));
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if (r)
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return r;
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@ -282,7 +239,6 @@ static int radeon_get_backend_map(struct radeon *radeon)
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return 0;
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}
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static int radeon_init_fence(struct radeon *radeon)
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{
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radeon->fence = 1;
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@ -307,7 +263,7 @@ static int handle_compare(void *key1, void *key2)
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return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
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}
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static struct radeon *radeon_new(struct radeon_winsys *rw)
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struct radeon *r600_drm_winsys_create(struct radeon_winsys *rw)
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{
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struct radeon *radeon;
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int r;
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@ -318,15 +274,10 @@ static struct radeon *radeon_new(struct radeon_winsys *rw)
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}
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rw->query_info(rw, &radeon->info);
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radeon->fd = radeon->info.fd;
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radeon->device = radeon->info.pci_id;
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radeon->num_backends = radeon->info.r600_num_backends;
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radeon->refcount = 1;
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radeon->minor_version = radeon->info.drm_minor;
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radeon->family = radeon_family_from_device(radeon->device);
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radeon->family = radeon_family_from_device(radeon->info.pci_id);
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if (radeon->family == CHIP_UNKNOWN) {
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fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device);
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fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->info.pci_id);
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return radeon_decref(radeon);
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}
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/* setup class */
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@ -373,20 +324,14 @@ static struct radeon *radeon_new(struct radeon_winsys *rw)
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break;
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default:
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fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
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__func__, radeon->device);
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__func__, radeon->info.pci_id);
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break;
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}
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if (radeon_drm_get_tiling(radeon))
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return NULL;
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/* get the GPU counter frequency, failure is non fatal */
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radeon_get_clock_crystal_freq(radeon);
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if (radeon->minor_version >= 9)
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radeon_get_num_backends(radeon);
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if (radeon->minor_version >= 11) {
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if (radeon->info.drm_minor >= 11) {
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radeon_get_num_tile_pipes(radeon);
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radeon_get_backend_map(radeon);
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}
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@ -406,18 +351,10 @@ static struct radeon *radeon_new(struct radeon_winsys *rw)
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return radeon;
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}
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struct radeon *r600_drm_winsys_create(struct radeon_winsys *rw)
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{
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return radeon_new(rw);
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}
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struct radeon *radeon_decref(struct radeon *radeon)
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{
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if (radeon == NULL)
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return NULL;
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if (--radeon->refcount > 0) {
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return NULL;
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}
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util_hash_table_destroy(radeon->bo_handles);
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pipe_mutex_destroy(radeon->bo_handles_mutex);
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@ -1621,7 +1621,7 @@ void r600_context_flush(struct r600_context *ctx)
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chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
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chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
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chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
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r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
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r = drmCommandWriteRead(ctx->radeon->info.fd, DRM_RADEON_CS, &drmib,
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sizeof(struct drm_radeon_cs));
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if (r) {
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fprintf(stderr, "radeon: The kernel rejected CS, "
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@ -45,9 +45,6 @@ struct r600_bo;
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struct radeon {
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struct radeon_info info;
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int fd;
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int refcount;
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unsigned device;
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unsigned family;
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enum chip_class chip_class;
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struct r600_tiling_info tiling_info;
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@ -55,12 +52,9 @@ struct radeon {
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unsigned fence;
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unsigned *cfence;
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struct r600_bo *fence_bo;
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unsigned clock_crystal_freq;
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unsigned num_backends;
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unsigned num_tile_pipes;
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unsigned backend_map;
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boolean backend_map_valid;
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unsigned minor_version;
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/* List of buffer handles and its mutex. */
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struct util_hash_table *bo_handles;
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@ -44,14 +44,14 @@ int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
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args.handle = bo->handle;
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args.offset = 0;
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args.size = (uint64_t)bo->size;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP,
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r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_MMAP,
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&args, sizeof(args));
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if (r) {
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fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n",
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bo, bo->handle, r);
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return r;
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}
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ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr);
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ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->info.fd, args.addr_ptr);
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if (ptr == MAP_FAILED) {
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fprintf(stderr, "%s failed to map bo\n", __func__);
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return -errno;
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@ -101,7 +101,7 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
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memset(&open_arg, 0, sizeof(open_arg));
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open_arg.name = handle;
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r = drmIoctl(radeon->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
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r = drmIoctl(radeon->info.fd, DRM_IOCTL_GEM_OPEN, &open_arg);
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if (r != 0) {
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free(bo);
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return NULL;
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@ -118,7 +118,7 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
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args.initial_domain = initial_domain;
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args.flags = 0;
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args.handle = 0;
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r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_CREATE,
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r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_CREATE,
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&args, sizeof(args));
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bo->handle = args.handle;
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if (r) {
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@ -153,7 +153,7 @@ static void radeon_bo_destroy(struct radeon *radeon, struct radeon_bo *bo)
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radeon_bo_fixed_unmap(radeon, bo);
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memset(&args, 0, sizeof(args));
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args.handle = bo->handle;
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drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args);
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drmIoctl(radeon->info.fd, DRM_IOCTL_GEM_CLOSE, &args);
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memset(bo, 0, sizeof(struct radeon_bo));
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free(bo);
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}
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@ -188,7 +188,7 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo)
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memset(&args, 0, sizeof(args));
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args.handle = bo->handle;
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do {
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ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_WAIT_IDLE,
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ret = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_WAIT_IDLE,
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&args, sizeof(args));
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} while (ret == -EBUSY);
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return ret;
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@ -213,7 +213,7 @@ int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain
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args.handle = bo->handle;
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args.domain = 0;
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ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_BUSY,
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ret = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_BUSY,
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&args, sizeof(args));
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*domain = args.domain;
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@ -229,7 +229,7 @@ int radeon_bo_get_tiling_flags(struct radeon *radeon,
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int ret;
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args.handle = bo->handle;
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ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_GET_TILING,
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ret = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_GET_TILING,
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&args, sizeof(args));
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if (ret)
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return ret;
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@ -247,7 +247,7 @@ int radeon_bo_get_name(struct radeon *radeon,
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int ret;
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flink.handle = bo->handle;
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ret = drmIoctl(radeon->fd, DRM_IOCTL_GEM_FLINK, &flink);
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ret = drmIoctl(radeon->info.fd, DRM_IOCTL_GEM_FLINK, &flink);
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if (ret)
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return ret;
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@ -41,12 +41,22 @@
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#include <xf86drm.h>
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#include <stdio.h>
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#ifndef RADEON_INFO_TILING_CONFIG
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#define RADEON_INFO_TILING_CONFIG 6
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#endif
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#ifndef RADEON_INFO_WANT_HYPERZ
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#define RADEON_INFO_WANT_HYPERZ 7
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#endif
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#ifndef RADEON_INFO_WANT_CMASK
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#define RADEON_INFO_WANT_CMASK 8
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#endif
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#ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
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#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
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#endif
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#ifndef RADEON_INFO_NUM_BACKENDS
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#define RADEON_INFO_NUM_BACKENDS 10
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#endif
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@ -107,7 +117,7 @@ static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
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}
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static boolean radeon_get_drm_value(int fd, unsigned request,
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const char *name, uint32_t *out)
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const char *errname, uint32_t *out)
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{
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struct drm_radeon_info info = {0};
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int retval;
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@ -116,9 +126,9 @@ static boolean radeon_get_drm_value(int fd, unsigned request,
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info.request = request;
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retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
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if (retval) {
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fprintf(stderr, "%s: Failed to get %s, error number %d\n",
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__func__, name, retval);
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if (retval && errname) {
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fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
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errname, retval);
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return FALSE;
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}
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return TRUE;
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@ -196,8 +206,8 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
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retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
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&gem_info, sizeof(gem_info));
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if (retval) {
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fprintf(stderr, "%s: Failed to get MM info, error number %d\n",
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__FUNCTION__, retval);
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fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
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retval);
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return FALSE;
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}
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ws->info.gart_size = gem_info.gart_size;
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@ -218,10 +228,18 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
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return FALSE;
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}
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else if (ws->gen == R600) {
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if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
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if (ws->info.drm_minor >= 9 &&
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!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
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"num backends",
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&ws->info.r600_num_backends))
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return FALSE;
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/* get the GPU counter frequency, failure is not fatal */
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radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
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&ws->info.r600_clock_crystal_freq);
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radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
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&ws->info.r600_tiling_config);
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}
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return TRUE;
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@ -83,6 +83,8 @@ struct radeon_info {
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uint32_t r300_num_z_pipes;
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uint32_t r600_num_backends;
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uint32_t r600_clock_crystal_freq;
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uint32_t r600_tiling_config;
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};
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enum radeon_feature_id {
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