From fa13b2f00214cbbf8d5cac05f5ffe7410f8f85a3 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 27 Aug 2019 09:01:02 +0200 Subject: [PATCH] radv/gfx10: always set ballot_mask_bits to 64 The codegen handles it and it adds the correct casts. This fixes a bunch of LLVM validation errors when enabling Wave32 for compute. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 047a77d6c96..27567317c8c 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -4185,8 +4185,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, AC_FLOAT_MODE_DEFAULT; ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class, - options->family, float_mode, options->wave_size, - options->wave_size); + options->family, float_mode, options->wave_size, 64); ctx.context = ctx.ac.context; radv_nir_shader_info_init(&shader_info->info);