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pan/mdg: Garbage collect silly quirk 

As discussed with Jason and Connor, this is probably subtly broken on
Mali T720.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
This commit is contained in:
Alyssa Rosenzweig 2021-07-23 11:44:35 -04:00 committed by Marge Bot
parent 7ecfbaf7f0
commit f9442e46ff
2 changed files with 3 additions and 11 deletions
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3
src/panfrost/midgard/midgard_compile.c
View File

@ -309,10 +309,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
nir_lower_tex_options lower_tex_options = {
.lower_txs_lod = true,
.lower_txp = ~0,
.lower_tex_without_implicit_lod =
(quirks & MIDGARD_EXPLICIT_LOD),
.lower_tg4_broadcom_swizzle = true,
/* TODO: we have native gradient.. */
.lower_txd = true,
};

11
src/panfrost/midgard/midgard_quirks.h
View File

@ -28,11 +28,7 @@
* may be errata requiring a workaround, or features. We're trying to be
* quirk-positive here; quirky is the best! */
/* Whether an explicit LOD is required via textureLod in a vertex shader. If
* set, vertex texturing will *always* textureLod. If unset, normal texture ops
* may be emitted in a vertex shader */
#define MIDGARD_EXPLICIT_LOD (1 << 0)
/* bit 0 unused */
/* Whether output texture registers (normally r28/r29) overlap with work
* registers r0/r1 and input texture registers (also normally r28/r29) overlap
@ -90,12 +86,11 @@ midgard_get_quirks(unsigned gpu_id)
return MIDGARD_INTERPIPE_REG_ALIASING;
case 0x750:
return MIDGARD_EXPLICIT_LOD |
MIDGARD_NO_UPPER_ALU;
return MIDGARD_NO_UPPER_ALU;
case 0x860:
case 0x880:
return MIDGARD_EXPLICIT_LOD;
return 0;
default:
unreachable("Invalid Midgard GPU ID");