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radv: add radv_clear_{cmask,dcc} helpers 

They will help for DCC MSAA textures and if we support mipmaps
in the future.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2018-04-06 12:22:02 +02:00
parent d899826733
commit f882c62218
4 changed files with 29 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -3617,9 +3617,7 @@ void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->cmask.offset,
image->cmask.size, value);
state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
@ -3651,9 +3649,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->dcc_offset,
image->surface.dcc_size, value);
state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;

5
src/amd/vulkan/radv_meta.h
View File

@ -195,6 +195,11 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
struct radv_image *linear_image);
uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
/* common nir builder helpers */
#include "nir/nir_builder.h"

27
src/amd/vulkan/radv_meta_clear.c
View File

@ -859,6 +859,24 @@ fail:
return res;
}
uint32_t
radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
{
return radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->cmask.offset,
image->cmask.size, value);
}
uint32_t
radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
{
return radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->dcc_offset,
image->surface.dcc_size, value);
}
static void vi_get_fast_clear_parameters(VkFormat format,
const VkClearColorValue *clear_value,
uint32_t* reset_value,
@ -1020,15 +1038,12 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
&clear_value, &reset_value,
&can_avoid_fast_clear_elim);
flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
iview->image->offset + iview->image->dcc_offset,
iview->image->surface.dcc_size, reset_value);
flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
!can_avoid_fast_clear_elim);
} else {
flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
iview->image->offset + iview->image->cmask.offset,
iview->image->cmask.size, 0);
flush_bits = radv_clear_cmask(cmd_buffer, iview->image, 0);
}
if (post_flush) {

4
src/amd/vulkan/radv_meta_fast_clear.c
View File

@ -771,9 +771,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
RADV_CMD_FLAG_INV_VMEM_L1;
state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->dcc_offset,
image->surface.dcc_size, 0xffffffff);
state->flush_bits |= radv_clear_dcc(cmd_buffer, image, 0xffffffff);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;