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freedreno/ir3: remove RA "q-values" optimization 

This is mainly the "piglit optimization" (ie, since piglit launches an
separate process for for each test).  It was never wired up for a6xx,
and makes register class setup unnecessarily complicated.  Remove it to
simplify the next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5431>
This commit is contained in:
Rob Clark 2020-06-11 14:56:29 -07:00 committed by Marge Bot
parent 562aaea07c
commit f80092dad2
1 changed files with 4 additions and 55 deletions
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59
src/freedreno/ir3/ir3_ra_regset.c
View File

@ -33,43 +33,6 @@
#include "ir3_compiler.h"
#include "ir3_ra.h"
static void
build_q_values(unsigned int **q_values, unsigned off,
const unsigned *sizes, unsigned count)
{
for (unsigned i = 0; i < count; i++) {
q_values[i + off] = rzalloc_array(q_values, unsigned, total_class_count);
/* From register_allocate.c:
*
* q(B,C) (indexed by C, B is this register class) in
* Runeson/Nyström paper. This is "how many registers of B could
* the worst choice register from C conflict with".
*
* If we just let the register allocation algorithm compute these
* values, is extremely expensive. However, since all of our
* registers are laid out, we can very easily compute them
* ourselves. View the register from C as fixed starting at GRF n
* somewhere in the middle, and the register from B as sliding back
* and forth. Then the first register to conflict from B is the
* one starting at n - class_size[B] + 1 and the last register to
* conflict will start at n + class_size[B] - 1. Therefore, the
* number of conflicts from B is class_size[B] + class_size[C] - 1.
*
* +-+-+-+-+-+-+ +-+-+-+-+-+-+
* B | | | | | |n| --> | | | | | | |
* +-+-+-+-+-+-+ +-+-+-+-+-+-+
* +-+-+-+-+-+
* C |n| | | | |
* +-+-+-+-+-+
*
* (Idea copied from brw_fs_reg_allocate.cpp)
*/
for (unsigned j = 0; j < count; j++)
q_values[i + off][j + off] = sizes[i] + sizes[j] - 1;
}
}
static void
setup_conflicts(struct ir3_ra_reg_set *set)
{
@ -210,26 +173,12 @@ ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
ra_add_transitive_reg_pair_conflict(set->regs, freg, hreg0, hreg1);
}
setup_conflicts(set);
// TODO also need to update q_values, but for now:
ra_set_finalize(set->regs, NULL);
} else {
setup_conflicts(set);
/* allocate and populate q_values: */
unsigned int **q_values = ralloc_array(set, unsigned *, total_class_count);
build_q_values(q_values, 0, class_sizes, class_count);
build_q_values(q_values, HALF_OFFSET, half_class_sizes, half_class_count);
build_q_values(q_values, HIGH_OFFSET, high_class_sizes, high_class_count);
ra_set_finalize(set->regs, q_values);
ralloc_free(q_values);
}
setup_conflicts(set);
ra_set_finalize(set->regs, NULL);
return set;
}