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st/glthread: allow for invalid L3 cache id. 

If we get 0xffffffff consider L3 cache info invalid and
don't continue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4496
Fixes: d8ea509965 ("util: completely rewrite and do AMD Zen L3 cache pinning correctly")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9782>
This commit is contained in:
Dave Airlie 2021-03-25 13:40:51 +10:00 committed by Marge Bot
parent b03cfad77a
commit f7acdb1d1d
4 changed files with 17 additions and 10 deletions
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13
src/mesa/main/glthread.c
View File

@ -223,12 +223,13 @@ _mesa_glthread_flush_batch(struct gl_context *ctx)
int cpu = util_get_current_cpu();
if (cpu >= 0) {
unsigned L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
util_set_thread_affinity(glthread->queue.threads[0],
util_get_cpu_caps()->L3_affinity_mask[L3_cache],
NULL, util_get_cpu_caps()->num_cpu_mask_bits);
ctx->Driver.PinDriverToL3Cache(ctx, L3_cache);
uint16_t L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
if (L3_cache != U_CPU_INVALID_L3) {
util_set_thread_affinity(glthread->queue.threads[0],
util_get_cpu_caps()->L3_affinity_mask[L3_cache],
NULL, util_get_cpu_caps()->num_cpu_mask_bits);
ctx->Driver.PinDriverToL3Cache(ctx, L3_cache);
}
}
}

10
src/mesa/state_tracker/st_draw.c
View File

@ -117,11 +117,13 @@ prepare_draw(struct st_context *st, struct gl_context *ctx)
int cpu = util_get_current_cpu();
if (cpu >= 0) {
struct pipe_context *pipe = st->pipe;
unsigned L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
uint16_t L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
pipe->set_context_param(pipe,
PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
L3_cache);
if (L3_cache != U_CPU_INVALID_L3) {
pipe->set_context_param(pipe,
PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
L3_cache);
}
}
}
}

2
src/util/u_cpu_detect.c
View File

@ -438,6 +438,8 @@ get_cpu_topology(void)
util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
util_cpu_caps.num_L3_caches = 1;
memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));
#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
/* AMD Zen */
if (util_cpu_caps.family >= CPU_AMD_ZEN1_ZEN2 &&

2
src/util/u_cpu_detect.h
View File

@ -105,6 +105,8 @@ struct util_cpu_caps_t {
util_affinity_mask *L3_affinity_mask;
};
#define U_CPU_INVALID_L3 0xffff
static inline const struct util_cpu_caps_t *
util_get_cpu_caps(void)
{