radeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM op
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
parent
bfcefcb3c7
commit
f7a85a8a0a
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@ -2800,7 +2800,8 @@ static LLVMValueRef image_fetch_coords(
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static void image_append_args(
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struct si_shader_context *ctx,
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struct lp_build_emit_data * emit_data,
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unsigned target)
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unsigned target,
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bool atomic)
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{
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LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
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LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
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@ -2808,7 +2809,8 @@ static void image_append_args(
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emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
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emit_data->args[emit_data->arg_count++] =
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tgsi_is_array_image(target) ? i1true : i1false; /* da */
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emit_data->args[emit_data->arg_count++] = i1false; /* glc */
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if (!atomic)
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emit_data->args[emit_data->arg_count++] = i1false; /* glc */
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emit_data->args[emit_data->arg_count++] = i1false; /* slc */
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}
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@ -2822,7 +2824,8 @@ static void buffer_append_args(
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struct si_shader_context *ctx,
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struct lp_build_emit_data *emit_data,
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LLVMValueRef rsrc,
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LLVMValueRef index)
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LLVMValueRef index,
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bool atomic)
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{
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struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
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struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
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@ -2836,7 +2839,8 @@ static void buffer_append_args(
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emit_data->args[emit_data->arg_count++] = rsrc;
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emit_data->args[emit_data->arg_count++] = index; /* vindex */
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emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* voffset */
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emit_data->args[emit_data->arg_count++] = i1false; /* glc */
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if (!atomic)
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emit_data->args[emit_data->arg_count++] = i1false; /* glc */
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emit_data->args[emit_data->arg_count++] = i1false; /* slc */
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}
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@ -2857,14 +2861,14 @@ static void load_fetch_args(
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coords = image_fetch_coords(bld_base, inst, 1);
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if (target == TGSI_TEXTURE_BUFFER) {
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buffer_append_args(ctx, emit_data, rsrc, coords);
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buffer_append_args(ctx, emit_data, rsrc, coords, false);
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} else {
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emit_data->args[0] = coords;
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emit_data->args[1] = rsrc;
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emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
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emit_data->arg_count = 3;
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image_append_args(ctx, emit_data, target);
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image_append_args(ctx, emit_data, target, false);
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}
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}
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@ -2930,7 +2934,7 @@ static void store_fetch_args(
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emit_data->args[0] = data;
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emit_data->arg_count = 1;
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buffer_append_args(ctx, emit_data, rsrc, coords);
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buffer_append_args(ctx, emit_data, rsrc, coords, false);
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} else {
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emit_data->args[0] = data;
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emit_data->args[1] = coords;
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@ -2938,7 +2942,7 @@ static void store_fetch_args(
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emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
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emit_data->arg_count = 4;
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image_append_args(ctx, emit_data, target);
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image_append_args(ctx, emit_data, target, false);
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}
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}
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@ -2973,6 +2977,83 @@ static void store_emit(
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}
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}
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static void atomic_fetch_args(
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data)
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{
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struct si_shader_context *ctx = si_shader_context(bld_base);
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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LLVMBuilderRef builder = gallivm->builder;
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const struct tgsi_full_instruction * inst = emit_data->inst;
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unsigned target = inst->Memory.Texture;
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LLVMValueRef data1, data2;
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LLVMValueRef coords;
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LLVMValueRef rsrc;
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LLVMValueRef tmp;
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emit_data->dst_type = bld_base->base.elem_type;
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image_fetch_rsrc(bld_base, &inst->Src[0], &rsrc);
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coords = image_fetch_coords(bld_base, inst, 1);
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tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
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data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
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if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
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tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
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data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
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}
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/* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
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* of arguments, which is reversed relative to TGSI (and GLSL)
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*/
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if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
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emit_data->args[emit_data->arg_count++] = data2;
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emit_data->args[emit_data->arg_count++] = data1;
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if (target == TGSI_TEXTURE_BUFFER) {
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buffer_append_args(ctx, emit_data, rsrc, coords, true);
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} else {
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emit_data->args[emit_data->arg_count++] = coords;
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emit_data->args[emit_data->arg_count++] = rsrc;
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image_append_args(ctx, emit_data, target, true);
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}
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}
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static void atomic_emit(
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const struct lp_build_tgsi_action *action,
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struct lp_build_tgsi_context *bld_base,
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struct lp_build_emit_data *emit_data)
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{
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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LLVMBuilderRef builder = gallivm->builder;
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const struct tgsi_full_instruction * inst = emit_data->inst;
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unsigned target = inst->Memory.Texture;
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char intrinsic_name[40];
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LLVMValueRef tmp;
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if (target == TGSI_TEXTURE_BUFFER) {
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snprintf(intrinsic_name, sizeof(intrinsic_name),
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"llvm.amdgcn.buffer.atomic.%s", action->intr_name);
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} else {
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char coords_type[8];
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build_int_type_name(LLVMTypeOf(emit_data->args[1]),
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coords_type, sizeof(coords_type));
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snprintf(intrinsic_name, sizeof(intrinsic_name),
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"llvm.amdgcn.image.atomic.%s.%s",
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action->intr_name, coords_type);
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}
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tmp = lp_build_intrinsic(
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builder, intrinsic_name, bld_base->uint_bld.elem_type,
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emit_data->args, emit_data->arg_count,
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LLVMNoUnwindAttribute);
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emit_data->output[emit_data->chan] =
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LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
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}
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static void resq_fetch_args(
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data)
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@ -5156,6 +5237,7 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
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LLVMTargetMachineRef tm)
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{
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struct lp_build_tgsi_context *bld_base;
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struct lp_build_tgsi_action tmpl;
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memset(ctx, 0, sizeof(*ctx));
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radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
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@ -5210,6 +5292,29 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
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bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
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bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
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tmpl.fetch_args = atomic_fetch_args;
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tmpl.emit = atomic_emit;
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bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
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bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
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bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
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bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
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bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
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bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
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bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
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bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
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bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
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bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
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bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
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bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
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bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
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bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
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