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i965/fs: Ignore actual latency pre-reg-alloc. 

We care about depth-until-program-end, as a proxy for "make sure I
schedule those early instructions that open up the other things that can
make progress while keeping register pressure low", not actual latency
(since we're relying on the post-register-alloc scheduling to actually
schedule for the hardware).

total instructions in shared programs: 1609931 -> 1609931 (0.00%)
instructions in affected programs:     0 -> 0
GAINED:                                55
LOST:                                  43

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Eric Anholt 2013-11-05 23:30:33 -08:00
parent 7c90947a0b
commit f72a0d99fe
1 changed files with 29 additions and 21 deletions
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50
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
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@ -56,29 +56,12 @@ using namespace brw;
static bool debug = false;
class instruction_scheduler;
class schedule_node : public exec_node
{
public:
schedule_node(backend_instruction *inst, const struct brw_context *brw)
{
this->inst = inst;
this->child_array_size = 0;
this->children = NULL;
this->child_latency = NULL;
this->child_count = 0;
this->parent_count = 0;
this->unblocked_time = 0;
this->cand_generation = 0;
/* We can't measure Gen6 timings directly but expect them to be much
* closer to Gen7 than Gen4.
*/
if (brw->gen >= 6)
set_latency_gen7(brw->is_haswell);
else
set_latency_gen4();
}
schedule_node(backend_instruction *inst, instruction_scheduler *sched);
void set_latency_gen4();
void set_latency_gen7(bool is_haswell);
@ -607,10 +590,35 @@ vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *b
return 0;
}
schedule_node::schedule_node(backend_instruction *inst,
instruction_scheduler *sched)
{
struct brw_context *brw = sched->bv->brw;
this->inst = inst;
this->child_array_size = 0;
this->children = NULL;
this->child_latency = NULL;
this->child_count = 0;
this->parent_count = 0;
this->unblocked_time = 0;
this->cand_generation = 0;
/* We can't measure Gen6 timings directly but expect them to be much
* closer to Gen7 than Gen4.
*/
if (!sched->post_reg_alloc)
this->latency = 1;
else if (brw->gen >= 6)
set_latency_gen7(brw->is_haswell);
else
set_latency_gen4();
}
void
instruction_scheduler::add_inst(backend_instruction *inst)
{
schedule_node *n = new(mem_ctx) schedule_node(inst, bv->brw);
schedule_node *n = new(mem_ctx) schedule_node(inst, this);
assert(!inst->is_head_sentinel());
assert(!inst->is_tail_sentinel());