i965/nir/vec4: Implement load_const intrinsic
Similar to fs_nir backend, a nir_local_values map will be filled with newly allocated registers as the load_const instrinsic instructions are processed. Later, get_nir_src() will fetch the registers from this map for sources that are ssa. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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@ -165,7 +165,7 @@ brw_create_nir(struct brw_context *brw,
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nir_print_shader(nir, stderr);
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}
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nir_convert_from_ssa(nir, true);
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nir_convert_from_ssa(nir, is_scalar);
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nir_validate_shader(nir);
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/* This is the last pass we run before we start emitting stuff. It
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@ -415,6 +415,7 @@ public:
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const glsl_type *type) = 0;
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dst_reg *nir_locals;
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dst_reg *nir_ssa_values;
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src_reg *nir_inputs;
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unsigned *nir_uniform_driver_location;
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dst_reg *nir_system_values;
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@ -250,6 +250,8 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
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nir_locals[reg->index] = dst_reg(GRF, alloc.allocate(array_elems));
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}
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nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);
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nir_emit_cf_list(&impl->body);
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}
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@ -332,7 +334,22 @@ vec4_visitor::nir_emit_instr(nir_instr *instr)
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void
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vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
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{
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/* @TODO: Not yet implemented */
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dst_reg reg = dst_reg(GRF, alloc.allocate(1));
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reg.type = BRW_REGISTER_TYPE_F;
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/* @FIXME: consider emitting vector operations to save some MOVs in
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* cases where the components are representable in 8 bits.
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* By now, we emit a MOV for each component.
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*/
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for (unsigned i = 0; i < instr->def.num_components; ++i) {
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reg.writemask = 1 << i;
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emit(MOV(reg, src_reg(instr->value.f[i])));
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}
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/* Set final writemask */
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reg.writemask = brw_writemask_for_size(instr->def.num_components);
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nir_ssa_values[instr->def.index] = reg;
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}
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void
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