i965/miptree: Represent w-tiled stencil surfaces with isl
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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@ -83,7 +83,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
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break;
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case GL_TEXTURE_3D:
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assert(mt);
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depth = MAX2(mt->logical_depth0, 1);
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depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
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MAX2(mt->logical_depth0, 1);
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/* fallthrough */
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default:
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surftype = translate_tex_target(gl_target);
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@ -94,7 +95,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
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lod = irb ? irb->mt_level - irb->mt->first_level : 0;
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if (mt) {
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if (mt && mt->surf.size > 0) {
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width = mt->surf.logical_level0_px.width;
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height = mt->surf.logical_level0_px.height;
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} else if (mt) {
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width = mt->logical_width0;
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height = mt->logical_height0;
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}
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@ -115,7 +115,7 @@ emit_depth_packets(struct brw_context *brw,
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(stencil_mt->surf.row_pitch - 1));
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OUT_RELOC64(stencil_mt->bo,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
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OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
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ADVANCE_BATCH();
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}
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@ -175,7 +175,8 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
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break;
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case GL_TEXTURE_3D:
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assert(mt);
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depth = MAX2(mt->logical_depth0, 1);
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depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
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MAX2(mt->logical_depth0, 1);
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surftype = translate_tex_target(gl_target);
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break;
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case GL_TEXTURE_1D_ARRAY:
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@ -198,7 +199,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
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lod = irb ? irb->mt_level - irb->mt->first_level : 0;
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if (mt) {
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if (mt && mt->surf.size > 0) {
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width = mt->surf.logical_level0_px.width;
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height = mt->surf.logical_level0_px.height;
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} else if (mt) {
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width = mt->logical_width0;
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height = mt->logical_height0;
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}
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@ -819,7 +819,7 @@ miptree_create(struct brw_context *brw,
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GLuint num_samples,
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uint32_t layout_flags)
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{
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if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
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if (format == MESA_FORMAT_S_UINT8)
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return make_surface(brw, target, format, first_level, last_level,
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width0, height0, depth0, num_samples,
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ISL_TILING_W_BIT,
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@ -963,7 +963,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
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uint32_t tiling, swizzle;
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const GLenum target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
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if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8) {
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if (format == MESA_FORMAT_S_UINT8) {
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mt = make_surface(brw, target, MESA_FORMAT_S_UINT8,
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0, 0, width, height, depth, 1,
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ISL_TILING_W_BIT,
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@ -2950,36 +2950,44 @@ intel_update_r8stencil(struct brw_context *brw,
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if (!src || brw->gen >= 8 || !src->r8stencil_needs_update)
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return;
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assert(src->surf.size > 0);
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if (!mt->r8stencil_mt) {
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const uint32_t r8stencil_flags =
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MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
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MIPTREE_LAYOUT_DISABLE_AUX;
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assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
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mt->r8stencil_mt = intel_miptree_create(brw,
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src->target,
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MESA_FORMAT_R_UINT8,
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src->first_level,
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src->last_level,
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src->logical_width0,
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src->logical_height0,
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src->logical_depth0,
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src->surf.samples,
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r8stencil_flags);
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mt->r8stencil_mt = intel_miptree_create(
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brw,
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src->target,
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MESA_FORMAT_R_UINT8,
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src->first_level, src->last_level,
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src->surf.logical_level0_px.width,
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src->surf.logical_level0_px.height,
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src->surf.dim == ISL_SURF_DIM_3D ?
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src->surf.logical_level0_px.depth :
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src->surf.logical_level0_px.array_len,
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src->surf.samples,
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r8stencil_flags);
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assert(mt->r8stencil_mt);
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}
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struct intel_mipmap_tree *dst = mt->r8stencil_mt;
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for (int level = src->first_level; level <= src->last_level; level++) {
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const unsigned depth = src->level[level].depth;
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const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
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minify(src->surf.phys_level0_sa.depth, level) :
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src->surf.phys_level0_sa.array_len;
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for (unsigned layer = 0; layer < depth; layer++) {
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brw_blorp_copy_miptrees(brw,
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src, level, layer,
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dst, level, layer,
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0, 0, 0, 0,
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minify(src->logical_width0, level),
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minify(src->logical_height0, level));
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minify(src->surf.logical_level0_px.width,
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level),
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minify(src->surf.logical_level0_px.height,
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level));
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}
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}
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