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i965/miptree: Represent w-tiled stencil surfaces with isl 

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen 2017-05-26 11:36:38 +03:00
parent c84cb81771
commit f69a2ffe44
3 changed files with 36 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mesa/drivers/dri/i965/gen7_misc_state.c
View File

@ -83,7 +83,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
depth = MAX2(mt->logical_depth0, 1);
depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
MAX2(mt->logical_depth0, 1);
/* fallthrough */
default:
surftype = translate_tex_target(gl_target);
@ -94,7 +95,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
if (mt) {
if (mt && mt->surf.size > 0) {
width = mt->surf.logical_level0_px.width;
height = mt->surf.logical_level0_px.height;
} else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}

10
src/mesa/drivers/dri/i965/gen8_depth_state.c
View File

@ -115,7 +115,7 @@ emit_depth_packets(struct brw_context *brw,
(stencil_mt->surf.row_pitch - 1));
OUT_RELOC64(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
ADVANCE_BATCH();
}
@ -175,7 +175,8 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
depth = MAX2(mt->logical_depth0, 1);
depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
MAX2(mt->logical_depth0, 1);
surftype = translate_tex_target(gl_target);
break;
case GL_TEXTURE_1D_ARRAY:
@ -198,7 +199,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
if (mt) {
if (mt && mt->surf.size > 0) {
width = mt->surf.logical_level0_px.width;
height = mt->surf.logical_level0_px.height;
} else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}

38
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

@ -819,7 +819,7 @@ miptree_create(struct brw_context *brw,
GLuint num_samples,
uint32_t layout_flags)
{
if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8)
if (format == MESA_FORMAT_S_UINT8)
return make_surface(brw, target, format, first_level, last_level,
width0, height0, depth0, num_samples,
ISL_TILING_W_BIT,
@ -963,7 +963,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t tiling, swizzle;
const GLenum target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
if (brw->gen == 6 && format == MESA_FORMAT_S_UINT8) {
if (format == MESA_FORMAT_S_UINT8) {
mt = make_surface(brw, target, MESA_FORMAT_S_UINT8,
0, 0, width, height, depth, 1,
ISL_TILING_W_BIT,
@ -2950,36 +2950,44 @@ intel_update_r8stencil(struct brw_context *brw,
if (!src || brw->gen >= 8 || !src->r8stencil_needs_update)
return;
assert(src->surf.size > 0);
if (!mt->r8stencil_mt) {
const uint32_t r8stencil_flags =
MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
MIPTREE_LAYOUT_DISABLE_AUX;
assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
mt->r8stencil_mt = intel_miptree_create(brw,
src->target,
MESA_FORMAT_R_UINT8,
src->first_level,
src->last_level,
src->logical_width0,
src->logical_height0,
src->logical_depth0,
src->surf.samples,
r8stencil_flags);
mt->r8stencil_mt = intel_miptree_create(
brw,
src->target,
MESA_FORMAT_R_UINT8,
src->first_level, src->last_level,
src->surf.logical_level0_px.width,
src->surf.logical_level0_px.height,
src->surf.dim == ISL_SURF_DIM_3D ?
src->surf.logical_level0_px.depth :
src->surf.logical_level0_px.array_len,
src->surf.samples,
r8stencil_flags);
assert(mt->r8stencil_mt);
}
struct intel_mipmap_tree *dst = mt->r8stencil_mt;
for (int level = src->first_level; level <= src->last_level; level++) {
const unsigned depth = src->level[level].depth;
const unsigned depth = src->surf.dim == ISL_SURF_DIM_3D ?
minify(src->surf.phys_level0_sa.depth, level) :
src->surf.phys_level0_sa.array_len;
for (unsigned layer = 0; layer < depth; layer++) {
brw_blorp_copy_miptrees(brw,
src, level, layer,
dst, level, layer,
0, 0, 0, 0,
minify(src->logical_width0, level),
minify(src->logical_height0, level));
minify(src->surf.logical_level0_px.width,
level),
minify(src->surf.logical_level0_px.height,
level));
}
}