KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/nir,i965: Move HW generation check for UBO pushing to i965 

Iris only runs on BDW+ and ANV already handles this by not even trying
on anything older than HSW.  The only driver benefiting from this common
check is i965.  Moving it out makes the pass more generic and if some
driver comes along which can push UBOs on IVB, it should work for that.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11145>
This commit is contained in:
Jason Ekstrand 2021-06-02 14:01:24 -05:00 committed by Marge Bot
parent 8251bd216e
commit f63410eee6
8 changed files with 28 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/intel/compiler/brw_nir_analyze_ubo_ranges.c
View File

@ -200,13 +200,6 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
const struct brw_vs_prog_key *vs_key,
struct brw_ubo_range out_ranges[4])
{
const struct intel_device_info *devinfo = compiler->devinfo;
if (devinfo->verx10 <= 70) {
memset(out_ranges, 0, 4 * sizeof(struct brw_ubo_range));
return;
}
void *mem_ctx = ralloc_context(NULL);
struct ubo_analysis_state state = {

6
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -1039,6 +1039,12 @@ brw_create_context(gl_api api,
brw->has_swizzling = screen->hw_has_swizzling;
/* We don't push UBOs on IVB and earlier because the restrictions on
* 3DSTATE_CONSTANT_* make it really annoying to use push constants
* without dynamic state base address.
*/
brw->can_push_ubos = devinfo->verx10 >= 75;
brw->isl_dev = screen->isl_dev;
brw->vs.base.stage = MESA_SHADER_VERTEX;

2
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -826,6 +826,8 @@ struct brw_context
bool has_separate_stencil;
bool has_swizzling;
bool can_push_ubos;
/** Derived stencil states. */
bool stencil_enabled;
bool stencil_two_sided;

6
src/mesa/drivers/dri/i965/brw_gs.c
View File

@ -104,8 +104,10 @@ brw_codegen_gs_prog(struct brw_context *brw,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &gp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
prog_data.base.base.ubo_ranges);
if (brw->can_push_ubos) {
brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
prog_data.base.base.ubo_ranges);
}
uint64_t outputs_written = nir->info.outputs_written;

6
src/mesa/drivers/dri/i965/brw_tcs.c
View File

@ -65,8 +65,10 @@ brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tcp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
prog_data.base.base.ubo_ranges);
if (brw->can_push_ubos) {
brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
prog_data.base.base.ubo_ranges);
}
} else {
/* Upload the Patch URB Header as the first two uniforms.
* Do the annoying scrambling so the shader doesn't have to.

6
src/mesa/drivers/dri/i965/brw_tes.c
View File

@ -57,8 +57,10 @@ brw_codegen_tes_prog(struct brw_context *brw,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tep->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
prog_data.base.base.ubo_ranges);
if (brw->can_push_ubos) {
brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
prog_data.base.base.ubo_ranges);
}
int st_index = -1;
if (INTEL_DEBUG & DEBUG_SHADER_TIME)

6
src/mesa/drivers/dri/i965/brw_vs.c
View File

@ -142,8 +142,10 @@ brw_codegen_vs_prog(struct brw_context *brw,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &vp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_VERTEX]);
brw_nir_analyze_ubo_ranges(compiler, nir, key,
prog_data.base.base.ubo_ranges);
if (brw->can_push_ubos) {
brw_nir_analyze_ubo_ranges(compiler, nir, key,
prog_data.base.base.ubo_ranges);
}
} else {
brw_nir_setup_arb_uniforms(mem_ctx, nir, &vp->program,
&prog_data.base.base);

6
src/mesa/drivers/dri/i965/brw_wm.c
View File

@ -94,8 +94,10 @@ brw_codegen_wm_prog(struct brw_context *brw,
if (!fp->program.is_arb_asm) {
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &fp->program,
&prog_data.base, true);
brw_nir_analyze_ubo_ranges(brw->screen->compiler, nir,
NULL, prog_data.base.ubo_ranges);
if (brw->can_push_ubos) {
brw_nir_analyze_ubo_ranges(brw->screen->compiler, nir,
NULL, prog_data.base.ubo_ranges);
}
} else {
brw_nir_setup_arb_uniforms(mem_ctx, nir, &fp->program, &prog_data.base);