ac/gpu_info: add detection of TMZ support
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
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@ -140,6 +140,41 @@ static uint32_t get_l2_cache_size(enum radeon_family family)
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}
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}
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static bool
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has_tmz_support(amdgpu_device_handle dev,
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struct radeon_info *info,
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struct amdgpu_gpu_info *amdinfo)
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{
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struct amdgpu_bo_alloc_request request = {0};
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int r;
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amdgpu_bo_handle bo;
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if (amdinfo->ids_flags & AMDGPU_IDS_FLAGS_TMZ)
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return true;
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/* AMDGPU_IDS_FLAGS_TMZ is supported starting from drm_minor 40 */
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if (info->drm_minor >= 40)
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return false;
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/* Find out ourselves if TMZ is enabled */
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if (info->chip_class < GFX9)
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return false;
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if (info->drm_minor < 36)
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return false;
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request.alloc_size = 256;
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request.phys_alignment = 1024;
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request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
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request.flags = AMDGPU_GEM_CREATE_ENCRYPTED;
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r = amdgpu_bo_alloc(dev, &request, &bo);
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if (r)
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return false;
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amdgpu_bo_free(bo);
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return true;
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}
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bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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struct amdgpu_gpu_info *amdinfo)
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{
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@ -499,6 +534,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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info->has_read_registers_query = true;
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info->has_scheduled_fence_dependency = info->drm_minor >= 28;
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info->mid_command_buffer_preemption_enabled = amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
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info->has_tmz_support = has_tmz_support(dev, info, amdinfo);
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info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
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info->num_render_backends = amdinfo->rb_pipes;
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@ -920,6 +956,7 @@ void ac_print_gpu_info(struct radeon_info *info)
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printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
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printf(" mid_command_buffer_preemption_enabled = %u\n",
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info->mid_command_buffer_preemption_enabled);
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printf(" has_tmz_support = %u\n", info->has_tmz_support);
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printf("Shader core info:\n");
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printf(" max_shader_clock = %i\n", info->max_shader_clock);
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@ -156,6 +156,7 @@ struct radeon_info {
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bool has_scheduled_fence_dependency;
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/* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
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bool mid_command_buffer_preemption_enabled;
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bool has_tmz_support;
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/* Shader cores. */
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uint32_t cu_mask[4][2];
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