freedreno/a3xx: add support for disabling depth clipping

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin 2015-04-24 21:44:05 -04:00
parent dffc1a0ae3
commit f5c1101996
3 changed files with 8 additions and 5 deletions

View File

@ -45,17 +45,18 @@ Note: some of the new features are only available with certain drivers.
<ul>
<li>GL_AMD_pinned_memory on r600, radeonsi</li>
<li>GL_ARB_clip_control on i965</li>
<li>GL_ARB_depth_clamp on freedreno</li>
<li>GL_ARB_draw_indirect, GL_ARB_multi_draw_indirect on r600</li>
<li>GL_ARB_draw_instanced on freedreno</li>
<li>GL_ARB_gpu_shader_fp64 on nvc0, softpipe</li>
<li>GL_ARB_gpu_shader5 on i965/gen8+</li>
<li>GL_ARB_instanced_arrays on freedreno</li>
<li>GL_ARB_pipeline_statistics_query on i965, nv50, nvc0, r600, radeonsi, softpipe</li>
<li>GL_ARB_uniform_buffer_object on freedreno</li>
<li>GL_EXT_draw_buffers2 on freedreno</li>
<li>GL_ARB_clip_control on i965</li>
<li>GL_ARB_program_interface_query (all drivers)</li>
<li>GL_ARB_texture_stencil8 on nv50, nvc0, r600, radeonsi, softpipe</li>
<li>GL_ARB_gpu_shader5 on i965/gen8+</li>
<li>GL_ARB_uniform_buffer_object on freedreno</li>
<li>GL_EXT_draw_buffers2 on freedreno</li>
</ul>
<h2>Bug fixes</h2>

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@ -97,6 +97,8 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
if (cso->offset_tri)
so->gras_su_mode_control |= A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET;
if (!cso->depth_clip)
so->gras_cl_clip_cntl |= A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE;
return so;
}

View File

@ -182,6 +182,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
return is_a3xx(screen);
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
@ -193,7 +194,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return (is_a3xx(screen) || is_a4xx(screen)) ? 130 : 120;
/* Unsupported features. */
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: