intel/genxml: Add gen12 tile cache flush bit
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
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@ -6364,6 +6364,7 @@
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<value name="GGTT" value="1"/>
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</field>
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<field name="Flush LLC" start="58" end="58" type="bool"/>
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<field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
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<field name="Address" start="66" end="111" type="address"/>
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<field name="Immediate Data" start="128" end="191" type="uint"/>
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</instruction>
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