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intel/genxml: Add gen12 tile cache flush bit 

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Jordan Justen 2017-09-08 19:08:21 -07:00 committed by Rafael Antognolli
parent 8678699918
commit f573cd4757
1 changed files with 1 additions and 0 deletions
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src/intel/genxml/gen12.xml
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@ -6364,6 +6364,7 @@
<value name="GGTT" value="1"/>
</field>
<field name="Flush LLC" start="58" end="58" type="bool"/>
<field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
<field name="Address" start="66" end="111" type="address"/>
<field name="Immediate Data" start="128" end="191" type="uint"/>
</instruction>