pan/midgard: offset_swizzle doesn't need dstsize
This argument should be omitted. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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9eac9389fb
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f538981384
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@ -76,15 +76,15 @@ struct phys_reg {
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* by dst_offset. TODO: vec8+ */
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* by dst_offset. TODO: vec8+ */
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static void
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static void
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offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset, unsigned dstsize)
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offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset)
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{
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{
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unsigned out[MIR_VEC_COMPONENTS];
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unsigned out[MIR_VEC_COMPONENTS];
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signed reg_comp = reg_offset / srcsize;
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signed reg_comp = reg_offset / srcsize;
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signed dst_comp = dst_offset / dstsize;
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signed dst_comp = dst_offset / srcsize;
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assert(reg_comp * srcsize == reg_offset);
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assert(reg_comp * srcsize == reg_offset);
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assert(dst_comp * dstsize == dst_offset);
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assert(dst_comp * srcsize == dst_offset);
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for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
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for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
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signed comp = MAX2(c - dst_comp, 0);
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signed comp = MAX2(c - dst_comp, 0);
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@ -750,7 +750,7 @@ install_registers_instr(
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GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
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GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
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dest.offset;
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dest.offset;
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offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset, dest.size);
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offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset);
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ins->registers.src1_reg = src1.reg;
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ins->registers.src1_reg = src1.reg;
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@ -770,7 +770,7 @@ install_registers_instr(
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} else {
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} else {
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midgard_vector_alu_src mod2 =
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midgard_vector_alu_src mod2 =
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vector_alu_from_unsigned(ins->alu.src2);
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vector_alu_from_unsigned(ins->alu.src2);
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offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset, dest.size);
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offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset);
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ins->alu.src2 = vector_alu_srco_unsigned(mod2);
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ins->alu.src2 = vector_alu_srco_unsigned(mod2);
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ins->registers.src2_reg = src2.reg;
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ins->registers.src2_reg = src2.reg;
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@ -792,12 +792,12 @@ install_registers_instr(
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assert(src.reg == 26 || src.reg == 27);
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assert(src.reg == 26 || src.reg == 27);
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ins->load_store.reg = src.reg - 26;
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ins->load_store.reg = src.reg - 26;
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offset_swizzle(ins->swizzle[0], src.offset, src.size, 0, 4);
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offset_swizzle(ins->swizzle[0], src.offset, src.size, 0);
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} else {
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} else {
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struct phys_reg dst = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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struct phys_reg dst = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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ins->load_store.reg = dst.reg;
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ins->load_store.reg = dst.reg;
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offset_swizzle(ins->swizzle[0], 0, 4, dst.offset, dst.size);
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offset_swizzle(ins->swizzle[0], 0, 4, dst.offset);
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mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
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mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
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}
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}
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@ -836,13 +836,13 @@ install_registers_instr(
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ins->texture.in_reg_full = 1;
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ins->texture.in_reg_full = 1;
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ins->texture.in_reg_upper = 0;
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ins->texture.in_reg_upper = 0;
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ins->texture.in_reg_select = coord.reg - 28;
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ins->texture.in_reg_select = coord.reg - 28;
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offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0, 4);
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offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0);
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/* Next, install the destination */
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/* Next, install the destination */
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ins->texture.out_full = 1;
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ins->texture.out_full = 1;
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ins->texture.out_upper = 0;
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ins->texture.out_upper = 0;
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ins->texture.out_reg_select = dest.reg - 28;
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ins->texture.out_reg_select = dest.reg - 28;
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offset_swizzle(ins->swizzle[0], 0, 4, dest.offset, dest.size);
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offset_swizzle(ins->swizzle[0], 0, 4, dest.offset);
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mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
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mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
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/* If there is a register LOD/bias, use it */
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/* If there is a register LOD/bias, use it */
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