ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Fixes: 91074bb11b
"radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
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4a9fd90e1e
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f4211e6f93
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@ -2434,6 +2434,16 @@ static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
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return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
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}
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static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
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{
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uint32_t new_mask = 0;
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for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
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if (mask & (1u << i))
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new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
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return new_mask;
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}
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static void visit_store_ssbo(struct ac_nir_context *ctx,
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nir_intrinsic_instr *instr)
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{
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@ -2455,6 +2465,8 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
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if (components_32bit > 1)
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data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
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writemask = widen_mask(writemask, elem_size_mult);
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base_data = ac_to_float(&ctx->ac, src_data);
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base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
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base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
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@ -2474,9 +2486,6 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
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count = 2;
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}
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start *= elem_size_mult;
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count *= elem_size_mult;
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if (count > 4) {
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writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
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count = 4;
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@ -3266,17 +3275,12 @@ visit_store_var(struct ac_nir_context *ctx,
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NULL, NULL, &const_index, &indir_index);
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if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
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int old_writemask = writemask;
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src = LLVMBuildBitCast(ctx->ac.builder, src,
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LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
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"");
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writemask = 0;
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for (unsigned chan = 0; chan < 4; chan++) {
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if (old_writemask & (1 << chan))
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writemask |= 3u << (2 * chan);
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}
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writemask = widen_mask(writemask, 2);
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}
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switch (instr->variables[0]->var->data.mode) {
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