r600g: only flush for the correct colorbuffer, not all of them.
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parent
7e5173d065
commit
f4020c66fd
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@ -304,6 +304,7 @@ static int r600_state_pm4_generic(struct radeon_state *state)
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static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int bufs_are_cbs)
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static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int bufs_are_cbs)
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{
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{
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unsigned i, j, add, size;
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unsigned i, j, add, size;
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uint32_t flags_cb;
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state->nreloc = 0;
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state->nreloc = 0;
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for (i = 0; i < state->nbo; i++) {
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for (i = 0; i < state->nbo; i++) {
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@ -318,11 +319,12 @@ static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int
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}
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}
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}
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}
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for (i = 0; i < state->nreloc; i++) {
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for (i = 0; i < state->nreloc; i++) {
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flags_cb = flags;
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size = (radeon_ws_bo_get_size(state->bo[state->reloc_bo_id[i]]) + 255) >> 8;
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size = (radeon_ws_bo_get_size(state->bo[state->reloc_bo_id[i]]) + 255) >> 8;
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state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
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state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
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if (bufs_are_cbs)
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if (bufs_are_cbs)
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flags |= S_0085F0_CB0_DEST_BASE_ENA(1 << i);
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flags_cb |= S_0085F0_CB0_DEST_BASE_ENA(1 << i);
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state->pm4[state->cpm4++] = flags;
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state->pm4[state->cpm4++] = flags_cb;
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state->pm4[state->cpm4++] = size;
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state->pm4[state->cpm4++] = size;
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state->pm4[state->cpm4++] = 0x00000000;
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state->pm4[state->cpm4++] = 0x00000000;
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state->pm4[state->cpm4++] = 0x0000000A;
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state->pm4[state->cpm4++] = 0x0000000A;
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