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radeonsi: store chip class in the pm4 struct 

Will be used for asic specific pm4 behavior.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-06-07 14:04:58 -04:00
parent 3a47f1945f
commit f2a9bd8084
5 changed files with 62 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/gallium/drivers/radeonsi/r600_hw_context.c
View File

@ -161,7 +161,11 @@ static void r600_flush_framebuffer(struct r600_context *ctx)
if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
return;
pm4 = CALLOC_STRUCT(si_pm4_state);
pm4 = si_pm4_alloc_state(ctx);
if (pm4 == NULL)
return;
si_cmd_surface_sync(pm4, S_0085F0_CB0_DEST_BASE_ENA(1) |
S_0085F0_CB1_DEST_BASE_ENA(1) |
S_0085F0_CB2_DEST_BASE_ENA(1) |

12
src/gallium/drivers/radeonsi/radeonsi_pm4.c
View File

@ -173,6 +173,18 @@ void si_pm4_free_state(struct r600_context *rctx,
FREE(state);
}
struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
return NULL;
pm4->chip_class = rctx->chip_class;
return pm4;
}
uint32_t si_pm4_sync_flags(struct r600_context *rctx)
{
uint32_t cp_coher_cntl = 0;

4
src/gallium/drivers/radeonsi/radeonsi_pm4.h
View File

@ -35,9 +35,12 @@
// forward defines
struct r600_context;
enum chip_class;
struct si_pm4_state
{
/* family specific handling */
enum chip_class chip_class;
/* PKT3_SET_*_REG handling */
unsigned last_opcode;
unsigned last_reg;
@ -83,6 +86,7 @@ void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state);
void si_pm4_free_state(struct r600_context *rctx,
struct si_pm4_state *state,
unsigned idx);
struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx);
uint32_t si_pm4_sync_flags(struct r600_context *rctx);
unsigned si_pm4_dirty_dw(struct r600_context *rctx);

32
src/gallium/drivers/radeonsi/si_state.c
View File

@ -158,7 +158,7 @@ static void si_update_fb_blend_state(struct r600_context *rctx)
if (blend == NULL)
return;
pm4 = CALLOC_STRUCT(si_pm4_state);
pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
@ -321,7 +321,7 @@ static void si_set_blend_color(struct pipe_context *ctx,
const struct pipe_blend_color *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
@ -342,7 +342,7 @@ static void si_set_clip_state(struct pipe_context *ctx,
const struct pipe_clip_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct pipe_constant_buffer cb;
if (pm4 == NULL)
@ -375,7 +375,7 @@ static void si_set_scissor_states(struct pipe_context *ctx,
const struct pipe_scissor_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t tl, br;
if (pm4 == NULL)
@ -457,7 +457,11 @@ static void si_update_fb_rs_state(struct r600_context *rctx)
return;
}
pm4 = CALLOC_STRUCT(si_pm4_state);
pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
/* FIXME some of those reg can be computed with cso */
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
@ -619,7 +623,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
*/
static void si_update_dsa_stencil_ref(struct r600_context *rctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct pipe_stencil_ref *ref = &rctx->stencil_ref;
struct si_state_dsa *dsa = rctx->queued.named.dsa;
@ -1969,7 +1973,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t tl, br;
int tl_x, tl_y, br_x, br_y;
@ -2491,7 +2495,7 @@ static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
unsigned user_data_reg)
{
struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
int i, j;
if (!count)
@ -2565,7 +2569,7 @@ static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned
unsigned user_data_reg)
{
struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t *border_color_table = NULL;
int i, j;
@ -2814,7 +2818,10 @@ static void si_set_polygon_stipple(struct pipe_context *ctx,
static void si_texture_barrier(struct pipe_context *ctx)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
si_pm4_inval_texture_cache(pm4);
si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
@ -2886,7 +2893,10 @@ void si_init_state_functions(struct r600_context *rctx)
void si_init_config(struct r600_context *rctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
si_cmd_context_control(pm4);

27
src/gallium/drivers/radeonsi/si_state_draw.c
View File

@ -46,7 +46,10 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
uint64_t va;
si_pm4_delete_state(rctx, vs, shader->pm4);
pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
si_pm4_inval_shader_cache(pm4);
@ -125,7 +128,10 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
uint64_t va;
si_pm4_delete_state(rctx, ps, shader->pm4);
pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
si_pm4_inval_shader_cache(pm4);
@ -283,7 +289,7 @@ static unsigned si_conv_pipe_prim(unsigned pprim)
static bool si_update_draw_info_state(struct r600_context *rctx,
const struct pipe_draw_info *info)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct si_shader *vs = &rctx->vs_shader->current->shader;
unsigned prim = si_conv_pipe_prim(info->mode);
unsigned ls_mask = 0;
@ -343,7 +349,7 @@ static void si_update_spi_map(struct r600_context *rctx)
{
struct si_shader *ps = &rctx->ps_shader->current->shader;
struct si_shader *vs = &rctx->vs_shader->current->shader;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
unsigned i, j, tmp;
for (i = 0; i < ps->ninput; i++) {
@ -527,7 +533,7 @@ static void si_constant_buffer_update(struct r600_context *rctx)
static void si_vertex_buffer_update(struct r600_context *rctx)
{
struct pipe_context *ctx = &rctx->context;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
bool bound[PIPE_MAX_ATTRIBS] = {};
unsigned i, count;
uint64_t va;
@ -587,7 +593,10 @@ static void si_state_draw(struct r600_context *rctx,
const struct pipe_draw_info *info,
const struct pipe_index_buffer *ib)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
/* queries need some special values
* (this is non-zero if any query is active) */
@ -678,7 +687,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
cp_coher_cntl = si_pm4_sync_flags(rctx);
if (cp_coher_cntl) {
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
si_cmd_surface_sync(pm4, cp_coher_cntl);
si_pm4_set_state(rctx, sync, pm4);
}