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i965: Rename intel_mip* to brw_mip*. 

With lots of indentation fixes.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
This commit is contained in:
Kenneth Graunke 2021-02-22 11:01:33 -08:00 committed by Marge Bot
parent 7f1a408407
commit f28f6175e5
30 changed files with 1044 additions and 1057 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

161
src/mesa/drivers/dri/i965/brw_blorp.c
View File

@ -118,7 +118,7 @@ brw_blorp_init(struct brw_context *brw)
static void
blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
const struct intel_mipmap_tree *mt,
const struct brw_mipmap_tree *mt,
enum isl_aux_usage aux_usage,
bool is_render_target,
unsigned *level,
@ -131,12 +131,12 @@ blorp_surf_for_miptree(struct brw_context *brw,
for (unsigned i = 0; i < num_layers; i++) {
for (unsigned s = 0; s < num_samples; s++) {
const unsigned phys_layer = (start_layer + i) * num_samples + s;
intel_miptree_check_level_layer(mt, *level, phys_layer);
brw_miptree_check_level_layer(mt, *level, phys_layer);
}
}
} else {
for (unsigned i = 0; i < num_layers; i++)
intel_miptree_check_level_layer(mt, *level, start_layer + i);
brw_miptree_check_level_layer(mt, *level, start_layer + i);
}
*surf = (struct blorp_surf) {
@ -153,7 +153,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
};
if (surf->aux_usage == ISL_AUX_USAGE_HIZ &&
!intel_miptree_level_has_hiz(mt, *level))
!brw_miptree_level_has_hiz(mt, *level))
surf->aux_usage = ISL_AUX_USAGE_NONE;
if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
@ -161,9 +161,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
* surface. Without one, it does nothing.
*/
surf->clear_color =
intel_miptree_get_clear_color(mt, (struct brw_bo **)
&surf->clear_color_addr.buffer,
&surf->clear_color_addr.offset);
brw_miptree_get_clear_color(mt, (struct brw_bo **)
&surf->clear_color_addr.buffer,
&surf->clear_color_addr.offset);
surf->aux_surf = &mt->aux_buf->surf;
surf->aux_addr = (struct blorp_address) {
@ -271,10 +271,10 @@ swizzle_to_scs(GLenum swizzle)
*/
void
brw_blorp_blit_miptrees(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
unsigned src_level, unsigned src_layer,
mesa_format src_format, int src_swizzle,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
unsigned dst_level, unsigned dst_layer,
mesa_format dst_format,
float src_x0, float src_y0,
@ -386,8 +386,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
enum isl_format src_isl_format =
brw_blorp_to_isl_format(brw, src_format, false);
enum isl_aux_usage src_aux_usage =
intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format,
0 /* The astc5x5 WA isn't needed */);
brw_miptree_texture_aux_usage(brw, src_mt, src_isl_format,
0 /* The astc5x5 WA isn't needed */);
/* We do format workarounds for some depth formats so we can't reliably
* sample with HiZ. One of these days, we should fix that.
*/
@ -395,17 +395,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
src_aux_usage = ISL_AUX_USAGE_NONE;
const bool src_clear_supported =
src_aux_usage != ISL_AUX_USAGE_NONE && src_mt->format == src_format;
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
src_aux_usage, src_clear_supported);
brw_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
src_aux_usage, src_clear_supported);
enum isl_format dst_isl_format =
brw_blorp_to_isl_format(brw, dst_format, true);
enum isl_aux_usage dst_aux_usage =
intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format,
false, false);
brw_miptree_render_aux_usage(brw, dst_mt, dst_isl_format, false, false);
const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
dst_aux_usage, dst_clear_supported);
brw_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
dst_aux_usage, dst_clear_supported);
struct blorp_surf src_surf, dst_surf;
blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
@ -431,15 +430,15 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
blorp_filter, mirror_x, mirror_y);
blorp_batch_finish(&batch);
intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
dst_aux_usage);
brw_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
dst_aux_usage);
}
void
brw_blorp_copy_miptrees(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
unsigned dst_level, unsigned dst_layer,
unsigned src_x, unsigned src_y,
unsigned dst_x, unsigned dst_y,
@ -458,7 +457,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
switch (src_mt->aux_usage) {
case ISL_AUX_USAGE_HIZ:
if (intel_miptree_sample_with_hiz(brw, src_mt)) {
if (brw_miptree_sample_with_hiz(brw, src_mt)) {
src_aux_usage = src_mt->aux_usage;
src_clear_supported = true;
} else {
@ -489,10 +488,10 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
break;
}
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
src_aux_usage, src_clear_supported);
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
dst_aux_usage, dst_clear_supported);
brw_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
src_aux_usage, src_clear_supported);
brw_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
dst_aux_usage, dst_clear_supported);
struct blorp_surf src_surf, dst_surf;
blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
@ -522,8 +521,8 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
dst_aux_usage);
brw_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
dst_aux_usage);
}
void
@ -547,10 +546,10 @@ brw_blorp_copy_buffers(struct brw_context *brw,
}
static struct intel_mipmap_tree *
static struct brw_mipmap_tree *
find_miptree(GLbitfield buffer_bit, struct brw_renderbuffer *irb)
{
struct intel_mipmap_tree *mt = irb->mt;
struct brw_mipmap_tree *mt = irb->mt;
if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
mt = mt->stencil_mt;
return mt;
@ -575,8 +574,8 @@ do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
const struct gl_context *ctx = &brw->ctx;
/* Find source/dst miptrees */
struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
struct brw_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
struct brw_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
const bool do_srgb = ctx->Color.sRGBEnabled;
@ -620,8 +619,8 @@ try_blorp_blit(struct brw_context *brw,
/* Find buffers */
struct brw_renderbuffer *src_irb;
struct brw_renderbuffer *dst_irb;
struct intel_mipmap_tree *src_mt;
struct intel_mipmap_tree *dst_mt;
struct brw_mipmap_tree *src_mt;
struct brw_mipmap_tree *dst_mt;
switch (buffer_bit) {
case GL_COLOR_BUFFER_BIT:
src_irb = brw_renderbuffer(read_fb->_ColorReadBuffer);
@ -709,8 +708,8 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
*/
intel_prepare_render(brw);
struct intel_mipmap_tree *src_mt = src_irb->mt;
struct intel_mipmap_tree *dst_mt = intel_image->mt;
struct brw_mipmap_tree *src_mt = src_irb->mt;
struct brw_mipmap_tree *dst_mt = intel_image->mt;
/* We can't handle any combined depth-stencil formats because we have to
* reinterpret as a color format.
@ -936,7 +935,7 @@ blorp_get_client_format(struct brw_context *brw,
bool
brw_blorp_upload_miptree(struct brw_context *brw,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
mesa_format dst_format,
uint32_t level, uint32_t x, uint32_t y, uint32_t z,
uint32_t width, uint32_t height, uint32_t depth,
@ -977,7 +976,7 @@ brw_blorp_upload_miptree(struct brw_context *brw,
src_image_stride = src_row_stride;
}
intel_miptree_check_level_layer(dst_mt, level, z + depth - 1);
brw_miptree_check_level_layer(dst_mt, level, z + depth - 1);
bool result = false;
@ -987,12 +986,12 @@ brw_blorp_upload_miptree(struct brw_context *brw,
* source alignment will do.
*/
for (unsigned i = 0; i < depth; ++i) {
struct intel_mipmap_tree *src_mt = intel_miptree_create_for_bo(
brw, src_bo, src_format,
src_offset + i * src_image_stride,
width, height, 1,
src_row_stride,
ISL_TILING_LINEAR, 0);
struct brw_mipmap_tree *src_mt =
brw_miptree_create_for_bo(brw, src_bo, src_format,
src_offset + i * src_image_stride,
width, height, 1,
src_row_stride,
ISL_TILING_LINEAR, 0);
if (!src_mt) {
perf_debug("intel_texsubimage: miptree creation for src failed\n");
@ -1016,7 +1015,7 @@ brw_blorp_upload_miptree(struct brw_context *brw,
GL_NEAREST, false, false, false, false);
}
intel_miptree_release(&src_mt);
brw_miptree_release(&src_mt);
}
result = true;
@ -1029,7 +1028,7 @@ err:
bool
brw_blorp_download_miptree(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
mesa_format src_format, uint32_t src_swizzle,
uint32_t level, uint32_t x, uint32_t y, uint32_t z,
uint32_t width, uint32_t height, uint32_t depth,
@ -1085,7 +1084,7 @@ brw_blorp_download_miptree(struct brw_context *brw,
dst_image_stride = dst_row_stride;
}
intel_miptree_check_level_layer(src_mt, level, z + depth - 1);
brw_miptree_check_level_layer(src_mt, level, z + depth - 1);
int y0 = y;
int y1 = y + height;
@ -1102,12 +1101,12 @@ brw_blorp_download_miptree(struct brw_context *brw,
* source alignment will do.
*/
for (unsigned i = 0; i < depth; ++i) {
struct intel_mipmap_tree *dst_mt = intel_miptree_create_for_bo(
brw, dst_bo, dst_format,
dst_offset + i * dst_image_stride,
width, height, 1,
dst_row_stride,
ISL_TILING_LINEAR, 0);
struct brw_mipmap_tree *dst_mt =
brw_miptree_create_for_bo(brw, dst_bo, dst_format,
dst_offset + i * dst_image_stride,
width, height, 1,
dst_row_stride,
ISL_TILING_LINEAR, 0);
if (!dst_mt) {
perf_debug("intel_texsubimage: miptree creation for src failed\n");
@ -1131,7 +1130,7 @@ brw_blorp_download_miptree(struct brw_context *brw,
GL_NEAREST, false, y_flip, false, false);
}
intel_miptree_release(&dst_mt);
brw_miptree_release(&dst_mt);
}
result = true;
@ -1252,7 +1251,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
*/
if (can_fast_clear && !irb->mt->aux_buf) {
assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
if (!intel_miptree_alloc_aux(brw, irb->mt)) {
if (!brw_miptree_alloc_aux(brw, irb->mt)) {
/* We're out of memory. Fall back to a non-fast clear. */
can_fast_clear = false;
}
@ -1260,7 +1259,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (can_fast_clear) {
const enum isl_aux_state aux_state =
intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
brw_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
union isl_color_value clear_color =
brw_meta_convert_fast_clear_color(brw, irb->mt,
&ctx->Color.ClearColor);
@ -1268,7 +1267,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
/* If the buffer is already in ISL_AUX_STATE_CLEAR and the clear color
* hasn't changed, the clear is redundant and can be skipped.
*/
if (!intel_miptree_set_clear_color(brw, irb->mt, clear_color) &&
if (!brw_miptree_set_clear_color(brw, irb->mt, clear_color) &&
aux_state == ISL_AUX_STATE_CLEAR) {
return;
}
@ -1308,18 +1307,17 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
* redundant clears.
*/
intel_miptree_set_aux_state(brw, irb->mt, irb->mt_level,
irb->mt_layer, num_layers,
ISL_AUX_STATE_CLEAR);
brw_miptree_set_aux_state(brw, irb->mt, irb->mt_level,
irb->mt_layer, num_layers,
ISL_AUX_STATE_CLEAR);
} else {
DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
enum isl_aux_usage aux_usage =
intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
false, false);
intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
num_layers, aux_usage);
brw_miptree_render_aux_usage(brw, irb->mt, isl_format, false, false);
brw_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
num_layers, aux_usage);
struct blorp_surf surf;
blorp_surf_for_miptree(brw, &surf, irb->mt, aux_usage, true,
@ -1336,8 +1334,8 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
clear_color, color_write_disable);
blorp_batch_finish(&batch);
intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
num_layers, aux_usage);
brw_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
num_layers, aux_usage);
}
return;
@ -1418,7 +1416,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
uint32_t level = 0, start_layer = 0, num_layers;
struct blorp_surf depth_surf, stencil_surf;
struct intel_mipmap_tree *depth_mt = NULL;
struct brw_mipmap_tree *depth_mt = NULL;
if (mask & BUFFER_BIT_DEPTH) {
struct brw_renderbuffer *irb = brw_renderbuffer(depth_rb);
depth_mt = find_miptree(GL_DEPTH_BUFFER_BIT, irb);
@ -1427,8 +1425,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
start_layer = irb->mt_layer;
num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
intel_miptree_prepare_depth(brw, depth_mt, level,
start_layer, num_layers);
brw_miptree_prepare_depth(brw, depth_mt, level, start_layer, num_layers);
unsigned depth_level = level;
blorp_surf_for_miptree(brw, &depth_surf, depth_mt, depth_mt->aux_usage,
@ -1437,7 +1434,7 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
}
uint8_t stencil_mask = 0;
struct intel_mipmap_tree *stencil_mt = NULL;
struct brw_mipmap_tree *stencil_mt = NULL;
if (mask & BUFFER_BIT_STENCIL) {
struct brw_renderbuffer *irb = brw_renderbuffer(stencil_rb);
stencil_mt = find_miptree(GL_STENCIL_BUFFER_BIT, irb);
@ -1454,9 +1451,9 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
intel_miptree_prepare_access(brw, stencil_mt, level, 1,
start_layer, num_layers,
ISL_AUX_USAGE_NONE, false);
brw_miptree_prepare_access(brw, stencil_mt, level, 1,
start_layer, num_layers,
ISL_AUX_USAGE_NONE, false);
unsigned stencil_level = level;
blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt,
@ -1476,19 +1473,19 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
blorp_batch_finish(&batch);
if (mask & BUFFER_BIT_DEPTH) {
intel_miptree_finish_depth(brw, depth_mt, level,
start_layer, num_layers, true);
brw_miptree_finish_depth(brw, depth_mt, level,
start_layer, num_layers, true);
}
if (stencil_mask) {
intel_miptree_finish_write(brw, stencil_mt, level,
start_layer, num_layers,
ISL_AUX_USAGE_NONE);
brw_miptree_finish_write(brw, stencil_mt, level,
start_layer, num_layers,
ISL_AUX_USAGE_NONE);
}
}
void
brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
brw_blorp_resolve_color(struct brw_context *brw, struct brw_mipmap_tree *mt,
unsigned level, unsigned layer,
enum isl_aux_op resolve_op)
{
@ -1528,7 +1525,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
void
brw_blorp_mcs_partial_resolve(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct brw_mipmap_tree *mt,
uint32_t start_layer, uint32_t num_layers)
{
DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
@ -1561,11 +1558,11 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw,
* - 7.5.3.3 Hierarchical Depth Buffer Resolve
*/
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
intel_hiz_exec(struct brw_context *brw, struct brw_mipmap_tree *mt,
unsigned int level, unsigned int start_layer,
unsigned int num_layers, enum isl_aux_op op)
{
assert(intel_miptree_level_has_hiz(mt, level));
assert(brw_miptree_level_has_hiz(mt, level));
assert(op != ISL_AUX_OP_NONE);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const char *opname = NULL;

18
src/mesa/drivers/dri/i965/brw_blorp.h
View File

@ -36,10 +36,10 @@ void brw_blorp_init(struct brw_context *brw);
void
brw_blorp_blit_miptrees(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
unsigned src_level, unsigned src_layer,
mesa_format src_format, int src_swizzle,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
unsigned dst_level, unsigned dst_layer,
mesa_format dst_format,
float src_x0, float src_y0,
@ -51,9 +51,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
void
brw_blorp_copy_miptrees(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
unsigned src_level, unsigned src_logical_layer,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
unsigned dst_level, unsigned dst_logical_layer,
unsigned src_x, unsigned src_y,
unsigned dst_x, unsigned dst_y,
@ -69,7 +69,7 @@ brw_blorp_copy_buffers(struct brw_context *brw,
bool
brw_blorp_upload_miptree(struct brw_context *brw,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
mesa_format dst_format,
uint32_t level, uint32_t x, uint32_t y, uint32_t z,
uint32_t width, uint32_t height, uint32_t depth,
@ -79,7 +79,7 @@ brw_blorp_upload_miptree(struct brw_context *brw,
bool
brw_blorp_download_miptree(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
mesa_format src_format, uint32_t src_swizzle,
uint32_t level, uint32_t x, uint32_t y, uint32_t z,
uint32_t width, uint32_t height, uint32_t depth,
@ -97,17 +97,17 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
void
brw_blorp_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct brw_mipmap_tree *mt,
unsigned level, unsigned layer,
enum isl_aux_op resolve_op);
void
brw_blorp_mcs_partial_resolve(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct brw_mipmap_tree *mt,
uint32_t start_layer, uint32_t num_layers);
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
intel_hiz_exec(struct brw_context *brw, struct brw_mipmap_tree *mt,
unsigned int level, unsigned int start_layer,
unsigned int num_layers, enum isl_aux_op op);

14
src/mesa/drivers/dri/i965/brw_clear.c
View File

@ -104,7 +104,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
struct gl_framebuffer *fb = ctx->DrawBuffer;
struct brw_renderbuffer *depth_irb =
intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_mipmap_tree *mt = depth_irb->mt;
struct brw_mipmap_tree *mt = depth_irb->mt;
struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
const struct gen_device_info *devinfo = &brw->screen->devinfo;
@ -179,7 +179,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
*/
if (mt->fast_clear_color.f32[0] != clear_value) {
for (uint32_t level = mt->first_level; level <= mt->last_level; level++) {
if (!intel_miptree_level_has_hiz(mt, level))
if (!brw_miptree_level_has_hiz(mt, level))
continue;
const unsigned level_layers = brw_get_num_logical_layers(mt, level);
@ -193,7 +193,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
enum isl_aux_state aux_state =
intel_miptree_get_aux_state(mt, level, layer);
brw_miptree_get_aux_state(mt, level, layer);
if (aux_state != ISL_AUX_STATE_CLEAR &&
aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
@ -209,18 +209,18 @@ brw_fast_clear_depth(struct gl_context *ctx)
*/
intel_hiz_exec(brw, mt, level, layer, 1,
ISL_AUX_OP_FULL_RESOLVE);
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
brw_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_RESOLVED);
}
}
const union isl_color_value clear_color = { .f32 = {clear_value, } };
intel_miptree_set_clear_color(brw, mt, clear_color);
brw_miptree_set_clear_color(brw, mt, clear_color);
}
for (unsigned a = 0; a < num_layers; a++) {
enum isl_aux_state aux_state =
intel_miptree_get_aux_state(mt, depth_irb->mt_level,
brw_miptree_get_aux_state(mt, depth_irb->mt_level,
depth_irb->mt_layer + a);
if (aux_state != ISL_AUX_STATE_CLEAR) {
@ -230,7 +230,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
}
intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
brw_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer, num_layers,
ISL_AUX_STATE_CLEAR);
return true;

46
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -1422,7 +1422,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
if (rb->mt->surf.samples == 1) {
assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
rb->layer_count == 1);
intel_miptree_prepare_external(brw, rb->mt);
brw_miptree_prepare_external(brw, rb->mt);
} else {
brw_renderbuffer_downsample(brw, rb);
@ -1439,7 +1439,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
* miptree without aux. However, that would be a lot of plumbing and
* this is a rather exotic case so it's not really worth it.
*/
intel_miptree_prepare_external(brw, rb->singlesample_mt);
brw_miptree_prepare_external(brw, rb->singlesample_mt);
}
}
}
@ -1693,7 +1693,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
* use of a mapping of the buffer involves a bunch of page faulting which is
* moderately expensive.
*/
struct intel_mipmap_tree *last_mt;
struct brw_mipmap_tree *last_mt;
if (num_samples == 0)
last_mt = rb->mt;
else
@ -1734,17 +1734,17 @@ intel_process_dri2_buffer(struct brw_context *brw,
uint32_t tiling, swizzle;
brw_bo_get_tiling(bo, &tiling, &swizzle);
struct intel_mipmap_tree *mt =
intel_miptree_create_for_bo(brw,
bo,
intel_rb_format(rb),
0,
drawable->w,
drawable->h,
1,
buffer->pitch,
isl_tiling_from_i915_tiling(tiling),
MIPTREE_CREATE_DEFAULT);
struct brw_mipmap_tree *mt =
brw_miptree_create_for_bo(brw,
bo,
intel_rb_format(rb),
0,
drawable->w,
drawable->h,
1,
buffer->pitch,
isl_tiling_from_i915_tiling(tiling),
MIPTREE_CREATE_DEFAULT);
if (!mt) {
brw_bo_unreference(bo);
return;
@ -1760,7 +1760,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
drawable->w, drawable->h,
buffer->pitch)) {
brw_bo_unreference(bo);
intel_miptree_release(&mt);
brw_miptree_release(&mt);
return;
}
@ -1809,7 +1809,7 @@ intel_update_image_buffer(struct brw_context *intel,
/* Check and see if we're already bound to the right
* buffer object
*/
struct intel_mipmap_tree *last_mt;
struct brw_mipmap_tree *last_mt;
if (num_samples == 0)
last_mt = rb->mt;
else
@ -1817,7 +1817,7 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo) {
if (buffer_type == __DRI_IMAGE_BUFFER_SHARED) {
intel_miptree_make_shareable(intel, last_mt);
brw_miptree_make_shareable(intel, last_mt);
}
return;
}
@ -1830,17 +1830,17 @@ intel_update_image_buffer(struct brw_context *intel,
*/
const bool allow_internal_aux = (num_samples == 0);
struct intel_mipmap_tree *mt =
intel_miptree_create_for_dri_image(intel, buffer, GL_TEXTURE_2D,
intel_rb_format(rb),
allow_internal_aux);
struct brw_mipmap_tree *mt =
brw_miptree_create_for_dri_image(intel, buffer, GL_TEXTURE_2D,
intel_rb_format(rb),
allow_internal_aux);
if (!mt)
return;
if (!intel_update_winsys_renderbuffer_miptree(intel, rb, mt,
buffer->width, buffer->height,
buffer->pitch)) {
intel_miptree_release(&mt);
brw_miptree_release(&mt);
return;
}
@ -1876,7 +1876,7 @@ intel_update_image_buffer(struct brw_context *intel,
* experience than any savings due to aux compression. But I've
* collected no data to prove my theory.
*/
intel_miptree_make_shareable(intel, mt);
brw_miptree_make_shareable(intel, mt);
}
}

2
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -1629,7 +1629,7 @@ gen6_upload_push_constants(struct brw_context *brw,
bool
gen9_use_linear_1d_layout(const struct brw_context *brw,
const struct intel_mipmap_tree *mt);
const struct brw_mipmap_tree *mt);
/* brw_queryformat.c */
void brw_query_internal_format(struct gl_context *ctx, GLenum target,

88
src/mesa/drivers/dri/i965/brw_draw.c
View File

@ -378,7 +378,7 @@ brw_merge_inputs(struct brw_context *brw)
static bool
intel_disable_rb_aux_buffer(struct brw_context *brw,
bool *draw_aux_buffer_disabled,
struct intel_mipmap_tree *tex_mt,
struct brw_mipmap_tree *tex_mt,
unsigned min_level, unsigned num_levels,
const char *usage)
{
@ -565,10 +565,10 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
"for sampling");
}
intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
min_level, num_levels,
min_layer, num_layers,
astc5x5_wa_bits);
brw_miptree_prepare_texture(brw, tex_obj->mt, view_format,
min_level, num_levels,
min_layer, num_layers,
astc5x5_wa_bits);
/* If any programs are using it with texelFetch, we may need to also do
* a prepare with an sRGB format to ensure texelFetch works "properly".
@ -577,10 +577,10 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
enum isl_format txf_format =
translate_tex_format(brw, tex_obj->_Format, GL_DECODE_EXT);
if (txf_format != view_format) {
intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
min_level, num_levels,
min_layer, num_layers,
astc5x5_wa_bits);
brw_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
min_level, num_levels,
min_layer, num_layers,
astc5x5_wa_bits);
}
}
@ -591,9 +591,9 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
intel_update_r8stencil(brw, tex_obj->mt);
}
if (intel_miptree_has_etc_shadow(brw, tex_obj->mt) &&
if (brw_miptree_has_etc_shadow(brw, tex_obj->mt) &&
tex_obj->mt->shadow_needs_update) {
intel_miptree_update_etc_shadow_levels(brw, tex_obj->mt);
brw_miptree_update_etc_shadow_levels(brw, tex_obj->mt);
}
}
@ -614,7 +614,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
"as a shader image");
}
intel_miptree_prepare_image(brw, tex_obj->mt);
brw_miptree_prepare_image(brw, tex_obj->mt);
brw_cache_flush_for_read(brw, tex_obj->mt->bo);
}
@ -633,10 +633,10 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
/* Resolve the depth buffer's HiZ buffer. */
depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
if (depth_irb && depth_irb->mt) {
intel_miptree_prepare_depth(brw, depth_irb->mt,
depth_irb->mt_level,
depth_irb->mt_layer,
depth_irb->layer_count);
brw_miptree_prepare_depth(brw, depth_irb->mt,
depth_irb->mt_level,
depth_irb->mt_layer,
depth_irb->layer_count);
}
/* Resolve color buffers for non-coherent framebuffer fetch. */
@ -655,10 +655,10 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
brw_renderbuffer(fb->_ColorDrawBuffers[i]);
if (irb) {
intel_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format,
irb->mt_level, 1,
irb->mt_layer, irb->layer_count,
brw->gen9_astc5x5_wa_tex_mask);
brw_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format,
irb->mt_level, 1,
irb->mt_layer, irb->layer_count,
brw->gen9_astc5x5_wa_tex_mask);
}
}
}
@ -676,17 +676,17 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
bool blend_enabled = ctx->Color.BlendEnabled & (1 << i);
enum isl_aux_usage aux_usage =
intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
blend_enabled,
draw_aux_buffer_disabled[i]);
brw_miptree_render_aux_usage(brw, irb->mt, isl_format,
blend_enabled,
draw_aux_buffer_disabled[i]);
if (brw->draw_aux_usage[i] != aux_usage) {
brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
brw->draw_aux_usage[i] = aux_usage;
}
intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
aux_usage);
brw_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
aux_usage);
brw_cache_flush_for_render(brw, irb->mt->bo,
isl_format, aux_usage);
@ -730,29 +730,29 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
if (depth_irb) {
bool depth_written = brw_depth_writes_enabled(brw);
if (depth_att->Layered) {
intel_miptree_finish_depth(brw, depth_irb->mt,
depth_irb->mt_level,
depth_irb->mt_layer,
depth_irb->layer_count,
depth_written);
brw_miptree_finish_depth(brw, depth_irb->mt,
depth_irb->mt_level,
depth_irb->mt_layer,
depth_irb->layer_count,
depth_written);
} else {
intel_miptree_finish_depth(brw, depth_irb->mt,
depth_irb->mt_level,
depth_irb->mt_layer, 1,
depth_written);
brw_miptree_finish_depth(brw, depth_irb->mt,
depth_irb->mt_level,
depth_irb->mt_layer, 1,
depth_written);
}
if (depth_written)
brw_depth_cache_add_bo(brw, depth_irb->mt->bo);
}
if (stencil_irb && brw->stencil_write_enabled) {
struct intel_mipmap_tree *stencil_mt =
struct brw_mipmap_tree *stencil_mt =
stencil_irb->mt->stencil_mt != NULL ?
stencil_irb->mt->stencil_mt : stencil_irb->mt;
brw_depth_cache_add_bo(brw, stencil_mt->bo);
intel_miptree_finish_write(brw, stencil_mt, stencil_irb->mt_level,
stencil_irb->mt_layer,
stencil_irb->layer_count, ISL_AUX_USAGE_NONE);
brw_miptree_finish_write(brw, stencil_mt, stencil_irb->mt_level,
stencil_irb->mt_layer,
stencil_irb->layer_count, ISL_AUX_USAGE_NONE);
}
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
@ -769,9 +769,9 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
brw_render_cache_add_bo(brw, irb->mt->bo, isl_format, aux_usage);
intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
aux_usage);
brw_miptree_finish_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
aux_usage);
}
}
@ -784,11 +784,11 @@ brw_renderbuffer_move_temp_back(struct brw_context *brw,
brw_cache_flush_for_read(brw, irb->align_wa_mt->bo);
intel_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
brw_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
irb->mt,
irb->Base.Base.TexImage->Level, irb->mt_layer);
intel_miptree_reference(&irb->align_wa_mt, NULL);
brw_miptree_reference(&irb->align_wa_mt, NULL);
/* Finally restore the x,y to correspond to full miptree. */
brw_renderbuffer_set_draw_offset(irb);

2
src/mesa/drivers/dri/i965/brw_generate_mipmap.c
View File

@ -77,7 +77,7 @@ brw_generate_mipmap(struct gl_context *ctx, GLenum target,
intel_finalize_mipmap_tree(brw, tex_obj);
}
struct intel_mipmap_tree *mt = intel_obj->mt;
struct brw_mipmap_tree *mt = intel_obj->mt;
if (!mt) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "mipmap generation");
return;

4
src/mesa/drivers/dri/i965/brw_meta_util.c
View File

@ -282,7 +282,7 @@ brw_meta_mirror_clip_and_scissor(const struct gl_context *ctx,
*/
bool
brw_is_color_fast_clear_compatible(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
const struct brw_mipmap_tree *mt,
const union gl_color_union *color)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
@ -329,7 +329,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
*/
union isl_color_value
brw_meta_convert_fast_clear_color(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
const struct brw_mipmap_tree *mt,
const union gl_color_union *color)
{
union isl_color_value override_color = {

4
src/mesa/drivers/dri/i965/brw_meta_util.h
View File

@ -44,12 +44,12 @@ brw_meta_mirror_clip_and_scissor(const struct gl_context *ctx,
union isl_color_value
brw_meta_convert_fast_clear_color(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
const struct brw_mipmap_tree *mt,
const union gl_color_union *color);
bool
brw_is_color_fast_clear_compatible(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
const struct brw_mipmap_tree *mt,
const union gl_color_union *color);
#ifdef __cplusplus

20
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@ -122,7 +122,7 @@ brw_depthbuffer_format(struct brw_context *brw)
return brw_depth_format(brw, drb->mt->format);
}
static struct intel_mipmap_tree *
static struct brw_mipmap_tree *
get_stencil_miptree(struct brw_renderbuffer *irb)
{
if (!irb)
@ -142,7 +142,7 @@ rebase_depth_stencil(struct brw_context *brw, struct brw_renderbuffer *irb,
isl_get_tile_masks(irb->mt->surf.tiling, irb->mt->cpp,
&tile_mask_x, &tile_mask_y);
assert(!intel_miptree_level_has_hiz(irb->mt, irb->mt_level));
assert(!brw_miptree_level_has_hiz(irb->mt, irb->mt_level));
uint32_t tile_x = irb->draw_x & tile_mask_x;
uint32_t tile_y = irb->draw_y & tile_mask_y;
@ -186,7 +186,7 @@ rebase_depth_stencil(struct brw_context *brw, struct brw_renderbuffer *irb,
brw->depthstencil.tile_x = tile_x;
brw->depthstencil.tile_y = tile_y;
brw->depthstencil.depth_offset = intel_miptree_get_aligned_offset(
brw->depthstencil.depth_offset = brw_miptree_get_aligned_offset(
irb->mt,
irb->draw_x & ~tile_mask_x,
irb->draw_y & ~tile_mask_y);
@ -203,7 +203,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
struct gl_framebuffer *fb = ctx->DrawBuffer;
struct brw_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct brw_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
struct intel_mipmap_tree *depth_mt = NULL;
struct brw_mipmap_tree *depth_mt = NULL;
bool invalidate_depth = clear_mask & BUFFER_BIT_DEPTH;
bool invalidate_stencil = clear_mask & BUFFER_BIT_STENCIL;
@ -237,7 +237,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
if (stencil_irb &&
stencil_irb != depth_irb &&
stencil_irb->mt == depth_mt) {
intel_miptree_reference(&stencil_irb->mt, depth_irb->mt);
brw_miptree_reference(&stencil_irb->mt, depth_irb->mt);
brw_renderbuffer_set_draw_offset(stencil_irb);
}
}
@ -257,9 +257,9 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
static void
brw_emit_depth_stencil_hiz(struct brw_context *brw,
struct brw_renderbuffer *depth_irb,
struct intel_mipmap_tree *depth_mt,
struct brw_mipmap_tree *depth_mt,
struct brw_renderbuffer *stencil_irb,
struct intel_mipmap_tree *stencil_mt)
struct brw_mipmap_tree *stencil_mt)
{
uint32_t tile_x = brw->depthstencil.tile_x;
uint32_t tile_y = brw->depthstencil.tile_y;
@ -327,8 +327,8 @@ brw_emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct brw_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct brw_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
struct intel_mipmap_tree *depth_mt = brw_renderbuffer_get_mt(depth_irb);
struct intel_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
struct brw_mipmap_tree *depth_mt = brw_renderbuffer_get_mt(depth_irb);
struct brw_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
if (depth_mt)
brw_cache_flush_for_depth(brw, depth_mt->bo);
@ -386,7 +386,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
if (!brw_renderbuffer_has_hiz(depth_irb)) {
/* Just because a miptree has ISL_AUX_USAGE_HIZ does not mean that
* all miplevels of that miptree are guaranteed to support HiZ. See
* intel_miptree_level_enable_hiz for details.
* brw_miptree_level_enable_hiz for details.
*/
info.hiz_usage = ISL_AUX_USAGE_NONE;
}

4
src/mesa/drivers/dri/i965/brw_object_purgeable.c
View File

@ -146,7 +146,7 @@ brw_texture_object_unpurgeable(struct gl_context * ctx,
return GL_UNDEFINED_APPLE;
if (option == GL_UNDEFINED_APPLE || !intel_bo_unpurgeable(intel->mt->bo)) {
intel_miptree_release(&intel->mt);
brw_miptree_release(&intel->mt);
return GL_UNDEFINED_APPLE;
}
@ -167,7 +167,7 @@ intel_render_object_unpurgeable(struct gl_context * ctx,
return GL_UNDEFINED_APPLE;
if (option == GL_UNDEFINED_APPLE || !intel_bo_unpurgeable(intel->mt->bo)) {
intel_miptree_release(&intel->mt);
brw_miptree_release(&intel->mt);
return GL_UNDEFINED_APPLE;
}

6
src/mesa/drivers/dri/i965/brw_surface_formats.c
View File

@ -231,7 +231,7 @@ brw_screen_init_surface_formats(struct brw_screen *screen)
* that they are renderable from an API perspective since core mesa will
* fall back to RGBA or RGBX (we can't render to non-power-of-two
* formats). For 8-bit, formats, this also keeps us from hitting some
* nasty corners in intel_miptree_map_blit if you ever try to map one.
* nasty corners in brw_miptree_map_blit if you ever try to map one.
*/
int format_size = _mesa_get_format_bytes(format);
if (format_size == 3 || format_size == 6)
@ -374,13 +374,13 @@ brw_screen_init_surface_formats(struct brw_screen *screen)
}
/* On hardware that lacks support for ETC1, we map ETC1 to RGBX
* during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
* during glCompressedTexImage2D(). See brw_mipmap_tree::wraps_etc1.
*/
screen->mesa_format_supports_texture[MESA_FORMAT_ETC1_RGB8] = true;
/* On hardware that lacks support for ETC2, we map ETC2 to a suitable
* MESA_FORMAT during glCompressedTexImage2D().
* See intel_mipmap_tree::wraps_etc2.
* See brw_mipmap_tree::wraps_etc2.
*/
screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8] = true;
screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8] = true;

40
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -78,7 +78,7 @@ brw_get_bo_mocs(const struct gen_device_info *devinfo, struct brw_bo *bo)
}
static void
get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
get_isl_surf(struct brw_context *brw, struct brw_mipmap_tree *mt,
GLenum target, struct isl_view *view,
uint32_t *tile_x, uint32_t *tile_y,
uint32_t *offset, struct isl_surf *surf)
@ -107,9 +107,9 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
assert(view->levels == 1 && view->array_len == 1);
assert(*tile_x == 0 && *tile_y == 0);
*offset += intel_miptree_get_tile_offsets(mt, view->base_level,
view->base_array_layer,
tile_x, tile_y);
*offset += brw_miptree_get_tile_offsets(mt, view->base_level,
view->base_array_layer,
tile_x, tile_y);
/* Minify the logical dimensions of the texture. */
const unsigned l = view->base_level - mt->first_level;
@ -135,7 +135,7 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
static void
brw_emit_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct brw_mipmap_tree *mt,
GLenum target, struct isl_view view,
enum isl_aux_usage aux_usage,
uint32_t *surf_offset, int surf_index,
@ -166,7 +166,7 @@ brw_emit_surface_state(struct brw_context *brw,
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
clear_color = intel_miptree_get_clear_color(mt, &clear_bo, &clear_offset);
clear_color = brw_miptree_get_clear_color(mt, &clear_bo, &clear_offset);
}
void *state = brw_state_batch(brw,
@ -234,7 +234,7 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
{
struct gl_context *ctx = &brw->ctx;
struct brw_renderbuffer *irb = brw_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
struct brw_mipmap_tree *mt = irb->mt;
assert(brw_render_target_supported(brw, rb));
@ -477,7 +477,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
} else {
struct brw_texture_object *intel_obj = brw_texture_object(obj);
struct intel_mipmap_tree *mt = intel_obj->mt;
struct brw_mipmap_tree *mt = intel_obj->mt;
if (plane > 0) {
if (mt->plane[plane - 1] == NULL)
@ -517,7 +517,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
* is safe because texture views aren't allowed on depth/stencil.
*/
mesa_fmt = mt->format;
} else if (intel_miptree_has_etc_shadow(brw, mt)) {
} else if (brw_miptree_has_etc_shadow(brw, mt)) {
mesa_fmt = mt->shadow_mt->format;
} else if (plane > 0) {
mesa_fmt = mt->format;
@ -578,7 +578,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
assert(mt->shadow_mt && !mt->shadow_needs_update);
mt = mt->shadow_mt;
format = ISL_FORMAT_R8_UINT;
} else if (intel_miptree_needs_fake_etc(brw, mt)) {
} else if (brw_miptree_needs_fake_etc(brw, mt)) {
assert(mt->shadow_mt && !mt->shadow_needs_update);
mt = mt->shadow_mt;
}
@ -611,8 +611,8 @@ static void brw_update_texture_surface(struct gl_context *ctx,
view.usage |= ISL_SURF_USAGE_CUBE_BIT;
enum isl_aux_usage aux_usage =
intel_miptree_texture_aux_usage(brw, mt, format,
brw->gen9_astc5x5_wa_tex_mask);
brw_miptree_texture_aux_usage(brw, mt, format,
brw->gen9_astc5x5_wa_tex_mask);
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
surf_offset, surf_index,
@ -909,7 +909,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
struct brw_renderbuffer *irb = brw_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
struct brw_mipmap_tree *mt = irb->mt;
uint32_t *surf;
uint32_t tile_x, tile_y;
enum isl_format format;
@ -1118,8 +1118,8 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
};
enum isl_aux_usage aux_usage =
intel_miptree_texture_aux_usage(brw, irb->mt, format,
brw->gen9_astc5x5_wa_tex_mask);
brw_miptree_texture_aux_usage(brw, irb->mt, format,
brw->gen9_astc5x5_wa_tex_mask);
if (brw->draw_aux_usage[i] == ISL_AUX_USAGE_NONE)
aux_usage = ISL_AUX_USAGE_NONE;
@ -1542,7 +1542,7 @@ update_image_surface(struct brw_context *brw,
} else {
struct brw_texture_object *intel_obj = brw_texture_object(obj);
struct intel_mipmap_tree *mt = intel_obj->mt;
struct brw_mipmap_tree *mt = intel_obj->mt;
unsigned base_layer, num_layers;
if (u->Layered) {
@ -1579,10 +1579,10 @@ update_image_surface(struct brw_context *brw,
} else {
const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
assert(!intel_miptree_has_color_unresolved(mt,
view.base_level, 1,
view.base_array_layer,
view.array_len));
assert(!brw_miptree_has_color_unresolved(mt,
view.base_level, 1,
view.base_array_layer,
view.array_len));
brw_emit_surface_state(brw, mt, mt->target, view,
ISL_AUX_USAGE_NONE,
surf_offset, surf_index,

86
src/mesa/drivers/dri/i965/intel_blit.c
View File

@ -40,9 +40,9 @@
#define FILE_DEBUG_FLAG DEBUG_BLIT
static void
intel_miptree_set_alpha_to_one(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int x, int y, int width, int height);
brw_miptree_set_alpha_to_one(struct brw_context *brw,
struct brw_mipmap_tree *mt,
int x, int y, int width, int height);
static GLuint translate_raster_op(enum gl_logicop_mode logicop)
{
@ -122,7 +122,7 @@ set_blitter_tiling(struct brw_context *brw,
ADVANCE_BATCH()
bool
intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
brw_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
{
/* The BLT doesn't handle sRGB conversion */
assert(src == _mesa_get_srgb_format_linear(src));
@ -145,7 +145,7 @@ intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
/* We can also discard alpha when going from A2->X2 for 2 bit alpha,
* however we can't fill the alpha channel with two 1 bits when going
* from X2->A2, because intel_miptree_set_alpha_to_one() is not yet
* from X2->A2, because brw_miptree_set_alpha_to_one() is not yet
* ready for this / can only handle 8 bit alpha.
*/
if (src == MESA_FORMAT_B10G10R10A2_UNORM)
@ -161,7 +161,7 @@ intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
static void
get_blit_intratile_offset_el(const struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct brw_mipmap_tree *mt,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
uint32_t *base_address_offset,
@ -372,9 +372,9 @@ emit_copy_blit(struct brw_context *brw,
static bool
emit_miptree_blit(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
uint32_t src_x, uint32_t src_y,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
uint32_t dst_x, uint32_t dst_y,
uint32_t width, uint32_t height,
bool reverse, enum gl_logicop_mode logicop)
@ -394,8 +394,8 @@ emit_miptree_blit(struct brw_context *brw,
* for linear surfaces and DWords for tiled surfaces. So the maximum
* pitch is 32k linear and 128k tiled.
*/
if (intel_miptree_blt_pitch(src_mt) >= 32768 ||
intel_miptree_blt_pitch(dst_mt) >= 32768) {
if (brw_miptree_blt_pitch(src_mt) >= 32768 ||
brw_miptree_blt_pitch(dst_mt) >= 32768) {
perf_debug("Falling back due to >= 32k/128k pitch\n");
return false;
}
@ -462,15 +462,15 @@ emit_miptree_blit(struct brw_context *brw,
* renderbuffers/textures.
*/
bool
intel_miptree_blit(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y, bool src_flip,
struct intel_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
enum gl_logicop_mode logicop)
brw_miptree_blit(struct brw_context *brw,
struct brw_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y, bool src_flip,
struct brw_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
enum gl_logicop_mode logicop)
{
/* The blitter doesn't understand multisampling at all. */
if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
@ -489,7 +489,7 @@ intel_miptree_blit(struct brw_context *brw,
* channel to 1.0 at the end. Also trivially ARGB2101010 to XRGB2101010,
* but not XRGB2101010 to ARGB2101010 yet.
*/
if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
if (!brw_miptree_blit_compatible_formats(src_format, dst_format)) {
perf_debug("%s: Can't use hardware blitter from %s to %s, "
"falling back.\n", __func__,
_mesa_get_format_name(src_format),
@ -500,8 +500,8 @@ intel_miptree_blit(struct brw_context *brw,
/* The blitter has no idea about HiZ or fast color clears, so we need to
* resolve the miptrees before we do anything.
*/
intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
brw_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
brw_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
if (src_flip) {
const unsigned h0 = src_mt->surf.phys_level0_sa.height;
@ -514,9 +514,9 @@ intel_miptree_blit(struct brw_context *brw,
}
uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
intel_miptree_get_image_offset(src_mt, src_level, src_slice,
brw_miptree_get_image_offset(src_mt, src_level, src_slice,
&src_image_x, &src_image_y);
intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
brw_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
&dst_image_x, &dst_image_y);
src_x += src_image_x;
src_y += src_image_y;
@ -532,23 +532,21 @@ intel_miptree_blit(struct brw_context *brw,
/* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
_mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
intel_miptree_set_alpha_to_one(brw, dst_mt,
dst_x, dst_y,
width, height);
brw_miptree_set_alpha_to_one(brw, dst_mt, dst_x, dst_y, width, height);
}
return true;
}
bool
intel_miptree_copy(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y,
struct intel_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y,
uint32_t src_width, uint32_t src_height)
brw_miptree_copy(struct brw_context *brw,
struct brw_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y,
struct brw_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y,
uint32_t src_width, uint32_t src_height)
{
/* The blitter doesn't understand multisampling at all. */
if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
@ -560,12 +558,12 @@ intel_miptree_copy(struct brw_context *brw,
/* The blitter has no idea about HiZ or fast color clears, so we need to
* resolve the miptrees before we do anything.
*/
intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
brw_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
brw_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
uint32_t src_image_x, src_image_y;
intel_miptree_get_image_offset(src_mt, src_level, src_slice,
&src_image_x, &src_image_y);
brw_miptree_get_image_offset(src_mt, src_level, src_slice,
&src_image_x, &src_image_y);
if (_mesa_is_format_compressed(src_mt->format)) {
GLuint bw, bh;
@ -596,8 +594,8 @@ intel_miptree_copy(struct brw_context *brw,
src_y += src_image_y;
uint32_t dst_image_x, dst_image_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
&dst_image_x, &dst_image_y);
brw_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
&dst_image_x, &dst_image_y);
if (_mesa_is_format_compressed(dst_mt->format)) {
GLuint bw, bh;
@ -707,9 +705,9 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
* miptree.
*/
static void
intel_miptree_set_alpha_to_one(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int x, int y, int width, int height)
brw_miptree_set_alpha_to_one(struct brw_context *brw,
struct brw_mipmap_tree *mt,
int x, int y, int width, int height)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
uint32_t BR13, CMD;

36
src/mesa/drivers/dri/i965/intel_blit.h
View File

@ -28,26 +28,26 @@
#include "brw_context.h"
bool intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst);
bool brw_miptree_blit_compatible_formats(mesa_format src, mesa_format dst);
bool intel_miptree_blit(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y, bool src_flip,
struct intel_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
enum gl_logicop_mode logicop);
bool brw_miptree_blit(struct brw_context *brw,
struct brw_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y, bool src_flip,
struct brw_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
enum gl_logicop_mode logicop);
bool intel_miptree_copy(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y,
struct intel_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y,
uint32_t src_width, uint32_t src_height);
bool brw_miptree_copy(struct brw_context *brw,
struct brw_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y,
struct brw_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y,
uint32_t src_width, uint32_t src_height);
bool
intelEmitImmediateColorExpandBlit(struct brw_context *brw,

8
src/mesa/drivers/dri/i965/intel_copy_image.c
View File

@ -36,9 +36,9 @@
static void
copy_miptrees(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
struct brw_mipmap_tree *src_mt,
int src_x, int src_y, int src_z, unsigned src_level,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
int dst_x, int dst_y, int dst_z, unsigned dst_level,
int src_width, int src_height)
{
@ -52,7 +52,7 @@ copy_miptrees(struct brw_context *brw,
* faster than using the 3D pipeline. Original Gen4 also has to rebase
* and copy miptree slices in order to render to unaligned locations.
*/
if (intel_miptree_copy(brw, src_mt, src_level, src_z, src_x, src_y,
if (brw_miptree_copy(brw, src_mt, src_level, src_z, src_x, src_y,
dst_mt, dst_level, dst_z, dst_x, dst_y,
src_width, src_height))
return;
@ -76,7 +76,7 @@ intel_copy_image_sub_data(struct gl_context *ctx,
int src_width, int src_height)
{
struct brw_context *brw = brw_context(ctx);
struct intel_mipmap_tree *src_mt, *dst_mt;
struct brw_mipmap_tree *src_mt, *dst_mt;
unsigned src_level, dst_level;
if (src_image) {

105
src/mesa/drivers/dri/i965/intel_fbo.c
View File

@ -61,8 +61,8 @@ intel_delete_renderbuffer(struct gl_context *ctx, struct gl_renderbuffer *rb)
assert(irb);
intel_miptree_release(&irb->mt);
intel_miptree_release(&irb->singlesample_mt);
brw_miptree_release(&irb->mt);
brw_miptree_release(&irb->singlesample_mt);
_mesa_delete_renderbuffer(ctx, rb);
}
@ -78,7 +78,7 @@ brw_renderbuffer_downsample(struct brw_context *brw,
{
if (!irb->need_downsample)
return;
intel_miptree_updownsample(brw, irb->mt, irb->singlesample_mt);
brw_miptree_updownsample(brw, irb->mt, irb->singlesample_mt);
irb->need_downsample = false;
}
@ -93,7 +93,7 @@ brw_renderbuffer_upsample(struct brw_context *brw,
{
assert(!irb->need_downsample);
intel_miptree_updownsample(brw, irb->singlesample_mt, irb->mt);
brw_miptree_updownsample(brw, irb->singlesample_mt, irb->mt);
}
/**
@ -111,7 +111,7 @@ intel_map_renderbuffer(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
struct brw_renderbuffer *irb = brw_renderbuffer(rb);
struct intel_mipmap_tree *mt;
struct brw_mipmap_tree *mt;
void *map;
ptrdiff_t stride;
@ -142,9 +142,9 @@ intel_map_renderbuffer(struct gl_context *ctx,
if (rb->NumSamples > 1) {
if (!irb->singlesample_mt) {
irb->singlesample_mt =
intel_miptree_create_for_renderbuffer(brw, irb->mt->format,
rb->Width, rb->Height,
1 /*num_samples*/);
brw_miptree_create_for_renderbuffer(brw, irb->mt->format,
rb->Width, rb->Height,
1 /*num_samples*/);
if (!irb->singlesample_mt)
goto fail;
irb->singlesample_mt_is_tmp = true;
@ -167,8 +167,8 @@ intel_map_renderbuffer(struct gl_context *ctx,
y = rb->Height - y - h;
}
intel_miptree_map(brw, mt, irb->mt_level, irb->mt_layer,
x, y, w, h, mode, &map, &stride);
brw_miptree_map(brw, mt, irb->mt_level, irb->mt_layer,
x, y, w, h, mode, &map, &stride);
if (flip_y) {
map += (h - 1) * stride;
@ -198,7 +198,7 @@ intel_unmap_renderbuffer(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
struct brw_renderbuffer *irb = brw_renderbuffer(rb);
struct intel_mipmap_tree *mt;
struct brw_mipmap_tree *mt;
DBG("%s: rb %d (%s)\n", __func__,
rb->Name, _mesa_get_format_name(rb->Format));
@ -215,7 +215,7 @@ intel_unmap_renderbuffer(struct gl_context *ctx,
mt = irb->mt;
}
intel_miptree_unmap(brw, mt, irb->mt_level, irb->mt_layer);
brw_miptree_unmap(brw, mt, irb->mt_level, irb->mt_layer);
if (irb->need_map_upsample) {
brw_renderbuffer_upsample(brw, irb);
@ -223,7 +223,7 @@ intel_unmap_renderbuffer(struct gl_context *ctx,
}
if (irb->singlesample_mt_is_tmp)
intel_miptree_release(&irb->singlesample_mt);
brw_miptree_release(&irb->singlesample_mt);
}
@ -295,7 +295,7 @@ intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_rend
rb->Height = height;
rb->_BaseFormat = _mesa_get_format_base_format(rb->Format);
intel_miptree_release(&irb->mt);
brw_miptree_release(&irb->mt);
DBG("%s: %s: %s (%dx%d)\n", __func__,
_mesa_enum_to_string(internalFormat),
@ -304,9 +304,9 @@ intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_rend
if (width == 0 || height == 0)
return true;
irb->mt = intel_miptree_create_for_renderbuffer(brw, rb->Format,
width, height,
MAX2(rb->NumSamples, 1));
irb->mt = brw_miptree_create_for_renderbuffer(brw, rb->Format,
width, height,
MAX2(rb->NumSamples, 1));
if (!irb->mt)
return false;
@ -392,15 +392,15 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
}
irb = brw_renderbuffer(rb);
intel_miptree_release(&irb->mt);
brw_miptree_release(&irb->mt);
/* Disable creation of the miptree's aux buffers because the driver exposes
* no EGL API to manage them. That is, there is no API for resolving the aux
* buffer's content to the main buffer nor for invalidating the aux buffer's
* content.
*/
irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
rb->Format, false);
irb->mt = brw_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
rb->Format, false);
if (!irb->mt)
return;
@ -534,7 +534,7 @@ brw_renderbuffer_update_wrapper(struct brw_context *brw,
{
struct gl_renderbuffer *rb = &irb->Base.Base;
struct brw_texture_image *intel_image = brw_texture_image(image);
struct intel_mipmap_tree *mt = intel_image->mt;
struct brw_mipmap_tree *mt = intel_image->mt;
int level = image->Level;
rb->AllocStorage = intel_nop_alloc_storage;
@ -543,7 +543,7 @@ brw_renderbuffer_update_wrapper(struct brw_context *brw,
layer += image->TexObject->Attrib.MinLayer;
level += image->TexObject->Attrib.MinLevel;
intel_miptree_check_level_layer(mt, level, layer);
brw_miptree_check_level_layer(mt, level, layer);
irb->mt_level = level;
irb->mt_layer = layer;
@ -557,7 +557,7 @@ brw_renderbuffer_update_wrapper(struct brw_context *brw,
mt->surf.logical_level0_px.array_len;
}
intel_miptree_reference(&irb->mt, mt);
brw_miptree_reference(&irb->mt, mt);
brw_renderbuffer_set_draw_offset(irb);
@ -570,10 +570,8 @@ brw_renderbuffer_set_draw_offset(struct brw_renderbuffer *irb)
unsigned int dst_x, dst_y;
/* compute offset of the particular 2D image within the texture region */
intel_miptree_get_image_offset(irb->mt,
irb->mt_level,
irb->mt_layer,
&dst_x, &dst_y);
brw_miptree_get_image_offset(irb->mt, irb->mt_level, irb->mt_layer,
&dst_x, &dst_y);
irb->draw_x = dst_x;
irb->draw_y = dst_y;
@ -595,7 +593,7 @@ intel_render_texture(struct gl_context * ctx,
struct brw_renderbuffer *irb = brw_renderbuffer(rb);
struct gl_texture_image *image = rb->TexImage;
struct brw_texture_image *intel_image = brw_texture_image(image);
struct intel_mipmap_tree *mt = intel_image->mt;
struct brw_mipmap_tree *mt = intel_image->mt;
int layer;
(void) fb;
@ -615,7 +613,7 @@ intel_render_texture(struct gl_context * ctx,
return;
}
intel_miptree_check_level_layer(mt, att->TextureLevel, layer);
brw_miptree_check_level_layer(mt, att->TextureLevel, layer);
if (!brw_renderbuffer_update_wrapper(brw, irb, image, layer, att->Layered)) {
_swrast_render_texture(ctx, fb, att);
@ -654,7 +652,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct brw_renderbuffer *stencilRb =
intel_get_renderbuffer(fb, BUFFER_STENCIL);
struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
struct brw_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
unsigned i;
DBG("%s() on fb %p (%s)\n", __func__,
@ -867,15 +865,15 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
return mask;
}
if (!intel_miptree_blit(brw,
src_irb->mt,
src_irb->mt_level, src_irb->mt_layer,
srcX0, srcY0, readFb->FlipY,
dst_irb->mt,
dst_irb->mt_level, dst_irb->mt_layer,
dstX0, dstY0, drawFb->FlipY,
dstX1 - dstX0, dstY1 - dstY0,
COLOR_LOGICOP_COPY)) {
if (!brw_miptree_blit(brw,
src_irb->mt,
src_irb->mt_level, src_irb->mt_layer,
srcX0, srcY0, readFb->FlipY,
dst_irb->mt,
dst_irb->mt_level, dst_irb->mt_layer,
dstX0, dstY0, drawFb->FlipY,
dstX1 - dstX0, dstY1 - dstY0,
COLOR_LOGICOP_COPY)) {
perf_debug("glBlitFramebuffer(): unknown blit failure. "
"Falling back to software rendering.\n");
return mask;
@ -955,7 +953,7 @@ intel_blit_framebuffer(struct gl_context *ctx,
bool
brw_renderbuffer_has_hiz(struct brw_renderbuffer *irb)
{
return intel_miptree_level_has_hiz(irb->mt, irb->mt_level);
return brw_miptree_level_has_hiz(irb->mt, irb->mt_level);
}
void
@ -965,26 +963,27 @@ brw_renderbuffer_move_to_temp(struct brw_context *brw,
{
struct gl_renderbuffer *rb =&irb->Base.Base;
struct brw_texture_image *intel_image = brw_texture_image(rb->TexImage);
struct intel_mipmap_tree *new_mt;
struct brw_mipmap_tree *new_mt;
int width, height, depth;
intel_get_image_dims(rb->TexImage, &width, &height, &depth);
assert(irb->align_wa_mt == NULL);
new_mt = intel_miptree_create(brw, GL_TEXTURE_2D,
intel_image->base.Base.TexFormat,
0, 0,
width, height, 1,
irb->mt->surf.samples,
MIPTREE_CREATE_BUSY);
new_mt = brw_miptree_create(brw, GL_TEXTURE_2D,
intel_image->base.Base.TexFormat,
0, 0,
width, height, 1,
irb->mt->surf.samples,
MIPTREE_CREATE_BUSY);
if (!invalidate)
intel_miptree_copy_slice(brw, intel_image->mt,
intel_image->base.Base.Level, irb->mt_layer,
new_mt, 0, 0);
if (!invalidate) {
brw_miptree_copy_slice(brw, intel_image->mt,
intel_image->base.Base.Level, irb->mt_layer,
new_mt, 0, 0);
}
intel_miptree_reference(&irb->align_wa_mt, new_mt);
intel_miptree_release(&new_mt);
brw_miptree_reference(&irb->align_wa_mt, new_mt);
brw_miptree_release(&new_mt);
irb->draw_x = 0;
irb->draw_y = 0;

14
src/mesa/drivers/dri/i965/intel_fbo.h
View File

@ -38,7 +38,7 @@
extern "C" {
#endif
struct intel_mipmap_tree;
struct brw_mipmap_tree;
/**
* Intel renderbuffer, derived from gl_renderbuffer.
@ -51,7 +51,7 @@ struct brw_renderbuffer
*
* This is multisampled if NumSamples is > 1.
*/
struct intel_mipmap_tree *mt;
struct brw_mipmap_tree *mt;
/**
* Downsampled contents for window-system MSAA renderbuffers.
@ -65,7 +65,7 @@ struct brw_renderbuffer
* or glCopyTexImage()), we just temporarily allocate singlesample_mt when
* asked to map the renderbuffer.
*/
struct intel_mipmap_tree *singlesample_mt;
struct brw_mipmap_tree *singlesample_mt;
/* Gen < 6 doesn't have layer specifier for render targets or depth. Driver
* needs to manually offset surfaces to correct level/layer. There are,
@ -75,7 +75,7 @@ struct brw_renderbuffer
*
* See brw_renderbuffer_move_to_temp().
*/
struct intel_mipmap_tree *align_wa_mt;
struct brw_mipmap_tree *align_wa_mt;
/**
* \name Miptree view
@ -146,7 +146,7 @@ brw_renderbuffer(struct gl_renderbuffer *rb)
return NULL;
}
static inline struct intel_mipmap_tree *
static inline struct brw_mipmap_tree *
brw_renderbuffer_get_mt(struct brw_renderbuffer *irb)
{
if (!irb)
@ -214,8 +214,8 @@ brw_renderbuffer_get_tile_offsets(struct brw_renderbuffer *irb,
return 0;
}
return intel_miptree_get_tile_offsets(irb->mt, irb->mt_level, irb->mt_layer,
tile_x, tile_y);
return brw_miptree_get_tile_offsets(irb->mt, irb->mt_level, irb->mt_layer,
tile_x, tile_y);
}
bool

971
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

File diff suppressed because it is too large Load Diff

294
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View File

@ -65,17 +65,17 @@ struct brw_texture_image;
/**
* This bit extends the set of GL_MAP_*_BIT enums.
*
* When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
* When calling brw_miptree_map() on an ETC-transcoded-to-RGB miptree or a
* depthstencil-split-to-separate-stencil miptree, we'll normally make a
* temporary and recreate the kind of data requested by Mesa core, since we're
* satisfying some glGetTexImage() request or something.
*
* However, occasionally you want to actually map the miptree's current data
* without transcoding back. This flag to intel_miptree_map() gets you that.
* without transcoding back. This flag to brw_miptree_map() gets you that.
*/
#define BRW_MAP_DIRECT_BIT 0x80000000
struct intel_miptree_map {
struct brw_miptree_map {
/** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
GLbitfield mode;
/** Region of interest for the map. */
@ -83,15 +83,15 @@ struct intel_miptree_map {
/** Possibly malloced temporary buffer for the mapping. */
void *buffer;
/** Possible pointer to a temporary linear miptree for the mapping. */
struct intel_mipmap_tree *linear_mt;
struct brw_mipmap_tree *linear_mt;
/** Pointer to the start of (map_x, map_y) returned by the mapping. */
void *ptr;
/** Stride of the mapping. */
int stride;
void (*unmap)(struct brw_context *brw,
struct intel_mipmap_tree *mt,
struct intel_miptree_map *map,
struct brw_mipmap_tree *mt,
struct brw_miptree_map *map,
unsigned int level,
unsigned int slice);
};
@ -99,7 +99,7 @@ struct intel_miptree_map {
/**
* Describes the location of each texture image within a miptree.
*/
struct intel_mipmap_level
struct brw_mipmap_level
{
/** Offset to this miptree level, used in computing x_offset. */
GLuint level_x;
@ -121,12 +121,12 @@ struct intel_mipmap_level
* This may be a list of cube faces, array slices in 2D array texture, or
* layers in a 3D texture. The list's length is \c depth.
*/
struct intel_mipmap_slice {
struct brw_mipmap_slice {
/**
* Mapping information. Persistent for the duration of
* intel_miptree_map/unmap on this slice.
* brw_miptree_map/unmap on this slice.
*/
struct intel_miptree_map *map;
struct brw_miptree_map *map;
} *slice;
};
@ -138,7 +138,7 @@ struct intel_mipmap_level
* handle all accesses to the buffer. Therefore we don't need the full miptree
* layout structure for this buffer.
*/
struct intel_miptree_aux_buffer
struct brw_miptree_aux_buffer
{
struct isl_surf surf;
@ -153,7 +153,7 @@ struct intel_miptree_aux_buffer
/**
* Offset into bo where the surface starts.
*
* @see intel_mipmap_aux_buffer::bo
* @see brw_mipmap_aux_buffer::bo
*
* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
* @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
@ -179,14 +179,14 @@ struct intel_miptree_aux_buffer
uint32_t clear_color_offset;
};
struct intel_mipmap_tree
struct brw_mipmap_tree
{
struct isl_surf surf;
/**
* Buffer object containing the surface.
*
* @see intel_mipmap_tree::offset
* @see brw_mipmap_tree::offset
* @see RENDER_SURFACE_STATE.SurfaceBaseAddress
* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
* @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
@ -229,12 +229,12 @@ struct intel_mipmap_tree
bool compressed;
/* Includes image offset tables: */
struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
struct brw_mipmap_level level[MAX_TEXTURE_LEVELS];
/**
* Offset into bo where the surface starts.
*
* @see intel_mipmap_tree::bo
* @see brw_mipmap_tree::bo
*
* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
* @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
@ -278,10 +278,10 @@ struct intel_mipmap_tree
* bits, regardless of mt->format.
*
* \see 3DSTATE_STENCIL_BUFFER
* \see intel_miptree_map_depthstencil()
* \see intel_miptree_unmap_depthstencil()
* \see brw_miptree_map_depthstencil()
* \see brw_miptree_unmap_depthstencil()
*/
struct intel_mipmap_tree *stencil_mt;
struct brw_mipmap_tree *stencil_mt;
/**
* \brief Shadow miptree for sampling when the main isn't supported by HW.
@ -294,7 +294,7 @@ struct intel_mipmap_tree
* - To store the decompressed ETC/EAC data in case we emulate the ETC
* compression on Gen 7 or earlier GPUs.
*/
struct intel_mipmap_tree *shadow_mt;
struct brw_mipmap_tree *shadow_mt;
bool shadow_needs_update;
/**
@ -318,14 +318,14 @@ struct intel_mipmap_tree
* depth clear behavior.
*
* To determine if HiZ is enabled, do not check this pointer. Instead,
* use intel_miptree_level_has_hiz().
* use brw_miptree_level_has_hiz().
*/
struct intel_miptree_aux_buffer *aux_buf;
struct brw_miptree_aux_buffer *aux_buf;
/**
* Planes 1 and 2 in case this is a planar surface.
*/
struct intel_mipmap_tree *plane[2];
struct brw_mipmap_tree *plane[2];
/**
* Fast clear color for this surface. For depth surfaces, the clear value
@ -346,10 +346,10 @@ struct intel_mipmap_tree
};
bool
intel_miptree_alloc_aux(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_alloc_aux(struct brw_context *brw,
struct brw_mipmap_tree *mt);
enum intel_miptree_create_flags {
enum brw_miptree_create_flags {
/** No miptree create flags */
MIPTREE_CREATE_DEFAULT = 0,
@ -364,47 +364,47 @@ enum intel_miptree_create_flags {
/** Create the miptree with auxiliary compression disabled
*
* This does not prevent the caller of intel_miptree_create from coming
* This does not prevent the caller of brw_miptree_create from coming
* along later and turning auxiliary compression back on but it does mean
* that the miptree will be created with mt->aux_usage == NONE.
*/
MIPTREE_CREATE_NO_AUX = 1 << 1,
};
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
GLenum target,
mesa_format format,
GLuint first_level,
GLuint last_level,
GLuint width0,
GLuint height0,
GLuint depth0,
GLuint num_samples,
enum intel_miptree_create_flags flags);
struct brw_mipmap_tree *brw_miptree_create(struct brw_context *brw,
GLenum target,
mesa_format format,
GLuint first_level,
GLuint last_level,
GLuint width0,
GLuint height0,
GLuint depth0,
GLuint num_samples,
enum brw_miptree_create_flags flags);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
struct brw_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
uint32_t height,
uint32_t depth,
int pitch,
enum isl_tiling tiling,
enum intel_miptree_create_flags flags);
struct brw_mipmap_tree *
brw_miptree_create_for_bo(struct brw_context *brw,
struct brw_bo *bo,
mesa_format format,
uint32_t offset,
uint32_t width,
uint32_t height,
uint32_t depth,
int pitch,
enum isl_tiling tiling,
enum brw_miptree_create_flags flags);
struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
mesa_format format,
bool allow_internal_aux);
struct brw_mipmap_tree *
brw_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
mesa_format format,
bool allow_internal_aux);
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct brw_renderbuffer *irb,
struct intel_mipmap_tree *singlesample_mt,
struct brw_mipmap_tree *singlesample_mt,
uint32_t width, uint32_t height,
uint32_t pitch);
@ -415,12 +415,12 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
* - There are no levels other than the base level 0.
* - Depth is 1.
*/
struct intel_mipmap_tree*
intel_miptree_create_for_renderbuffer(struct brw_context *brw,
mesa_format format,
uint32_t width,
uint32_t height,
uint32_t num_samples);
struct brw_mipmap_tree*
brw_miptree_create_for_renderbuffer(struct brw_context *brw,
mesa_format format,
uint32_t width,
uint32_t height,
uint32_t num_samples);
mesa_format
intel_depth_format_for_depthstencil_format(mesa_format format);
@ -429,28 +429,28 @@ mesa_format
intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
unsigned
brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
brw_get_num_logical_layers(const struct brw_mipmap_tree *mt, unsigned level);
/** \brief Assert that the level and layer are valid for the miptree. */
void
intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
brw_miptree_check_level_layer(const struct brw_mipmap_tree *mt,
uint32_t level,
uint32_t layer);
void intel_miptree_reference(struct intel_mipmap_tree **dst,
struct intel_mipmap_tree *src);
void brw_miptree_reference(struct brw_mipmap_tree **dst,
struct brw_mipmap_tree *src);
void intel_miptree_release(struct intel_mipmap_tree **mt);
void brw_miptree_release(struct brw_mipmap_tree **mt);
/* Check if an image fits an existing mipmap tree layout
*/
bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
bool brw_miptree_match_image(struct brw_mipmap_tree *mt,
struct gl_texture_image *image);
void
intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt,
GLuint level, GLuint slice,
GLuint *x, GLuint *y);
brw_miptree_get_image_offset(const struct brw_mipmap_tree *mt,
GLuint level, GLuint slice,
GLuint *x, GLuint *y);
enum isl_surf_dim
get_isl_surf_dim(GLenum target);
@ -464,25 +464,25 @@ intel_get_image_dims(struct gl_texture_image *image,
int *width, int *height, int *depth);
uint32_t
intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
brw_miptree_get_tile_offsets(const struct brw_mipmap_tree *mt,
GLuint level, GLuint slice,
uint32_t *tile_x,
uint32_t *tile_y);
uint32_t
intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
brw_miptree_get_aligned_offset(const struct brw_mipmap_tree *mt,
uint32_t x, uint32_t y);
void
intel_miptree_copy_slice(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
brw_miptree_copy_slice(struct brw_context *brw,
struct brw_mipmap_tree *src_mt,
unsigned src_level, unsigned src_layer,
struct intel_mipmap_tree *dst_mt,
struct brw_mipmap_tree *dst_mt,
unsigned dst_level, unsigned dst_layer);
void
intel_miptree_copy_teximage(struct brw_context *brw,
brw_miptree_copy_teximage(struct brw_context *brw,
struct brw_texture_image *intelImage,
struct intel_mipmap_tree *dst_mt);
struct brw_mipmap_tree *dst_mt);
/**
* \name Miptree HiZ functions
@ -493,12 +493,12 @@ intel_miptree_copy_teximage(struct brw_context *brw,
*/
bool
intel_miptree_level_has_hiz(const struct intel_mipmap_tree *mt, uint32_t level);
brw_miptree_level_has_hiz(const struct brw_mipmap_tree *mt, uint32_t level);
/**\}*/
bool
intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
brw_miptree_has_color_unresolved(const struct brw_mipmap_tree *mt,
unsigned start_level, unsigned num_levels,
unsigned start_layer, unsigned num_layers);
@ -532,8 +532,8 @@ intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
* compression format
*/
void
intel_miptree_prepare_access(struct brw_context *brw,
struct intel_mipmap_tree *mt,
brw_miptree_prepare_access(struct brw_context *brw,
struct brw_mipmap_tree *mt,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_usage aux_usage,
@ -545,7 +545,7 @@ intel_miptree_prepare_access(struct brw_context *brw,
* This will update the miptree's compression state so that future resolves
* happen correctly. Technically, this function can be called before the
* write occurs but the caller must ensure that they don't interlace
* intel_miptree_prepare_access and intel_miptree_finish_write calls to
* brw_miptree_prepare_access and brw_miptree_finish_write calls to
* overlapping layer/level ranges.
*
* \param[in] level The mip level that was written
@ -560,14 +560,14 @@ intel_miptree_prepare_access(struct brw_context *brw,
* auxiliary compression enabled
*/
void
intel_miptree_finish_write(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
brw_miptree_finish_write(struct brw_context *brw,
struct brw_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_usage aux_usage);
/** Get the auxiliary compression state of a miptree slice */
enum isl_aux_state
intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
brw_miptree_get_aux_state(const struct brw_mipmap_tree *mt,
uint32_t level, uint32_t layer);
/** Set the auxiliary compression state of a miptree slice range
@ -576,11 +576,11 @@ intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
* range of a miptree. It only modifies data structures and does not do any
* resolves. This should only be called by code which directly performs
* compression operations such as fast clears and resolves. Most code should
* use intel_miptree_prepare_access or intel_miptree_finish_write.
* use brw_miptree_prepare_access or brw_miptree_finish_write.
*/
void
intel_miptree_set_aux_state(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
brw_miptree_set_aux_state(struct brw_context *brw,
struct brw_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_state aux_state);
@ -592,115 +592,115 @@ intel_miptree_set_aux_state(struct brw_context *brw,
* using it with the blitter.
*/
static inline void
intel_miptree_access_raw(struct brw_context *brw,
struct intel_mipmap_tree *mt,
brw_miptree_access_raw(struct brw_context *brw,
struct brw_mipmap_tree *mt,
uint32_t level, uint32_t layer,
bool write)
{
intel_miptree_prepare_access(brw, mt, level, 1, layer, 1,
brw_miptree_prepare_access(brw, mt, level, 1, layer, 1,
ISL_AUX_USAGE_NONE, false);
if (write)
intel_miptree_finish_write(brw, mt, level, layer, 1, ISL_AUX_USAGE_NONE);
brw_miptree_finish_write(brw, mt, level, layer, 1, ISL_AUX_USAGE_NONE);
}
enum isl_aux_usage
intel_miptree_texture_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
brw_miptree_texture_aux_usage(struct brw_context *brw,
struct brw_mipmap_tree *mt,
enum isl_format view_format,
enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
void
intel_miptree_prepare_texture(struct brw_context *brw,
struct intel_mipmap_tree *mt,
brw_miptree_prepare_texture(struct brw_context *brw,
struct brw_mipmap_tree *mt,
enum isl_format view_format,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
void
intel_miptree_prepare_image(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_prepare_image(struct brw_context *brw,
struct brw_mipmap_tree *mt);
enum isl_aux_usage
intel_miptree_render_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
brw_miptree_render_aux_usage(struct brw_context *brw,
struct brw_mipmap_tree *mt,
enum isl_format render_format,
bool blend_enabled,
bool draw_aux_disabled);
void
intel_miptree_prepare_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
brw_miptree_prepare_render(struct brw_context *brw,
struct brw_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
enum isl_aux_usage aux_usage);
void
intel_miptree_finish_render(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
brw_miptree_finish_render(struct brw_context *brw,
struct brw_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
enum isl_aux_usage aux_usage);
void
intel_miptree_prepare_depth(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
brw_miptree_prepare_depth(struct brw_context *brw,
struct brw_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count);
void
intel_miptree_finish_depth(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
brw_miptree_finish_depth(struct brw_context *brw,
struct brw_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
bool depth_written);
void
intel_miptree_prepare_external(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_prepare_external(struct brw_context *brw,
struct brw_mipmap_tree *mt);
void
intel_miptree_finish_external(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_finish_external(struct brw_context *brw,
struct brw_mipmap_tree *mt);
void
intel_miptree_make_shareable(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_make_shareable(struct brw_context *brw,
struct brw_mipmap_tree *mt);
void
intel_miptree_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
brw_miptree_updownsample(struct brw_context *brw,
struct brw_mipmap_tree *src,
struct brw_mipmap_tree *dst);
void
intel_update_r8stencil(struct brw_context *brw,
struct intel_mipmap_tree *mt);
struct brw_mipmap_tree *mt);
void
intel_miptree_map(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level,
unsigned int slice,
unsigned int x,
unsigned int y,
unsigned int w,
unsigned int h,
GLbitfield mode,
void **out_ptr,
ptrdiff_t *out_stride);
brw_miptree_map(struct brw_context *brw,
struct brw_mipmap_tree *mt,
unsigned int level,
unsigned int slice,
unsigned int x,
unsigned int y,
unsigned int w,
unsigned int h,
GLbitfield mode,
void **out_ptr,
ptrdiff_t *out_stride);
void
intel_miptree_unmap(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level,
unsigned int slice);
brw_miptree_unmap(struct brw_context *brw,
struct brw_mipmap_tree *mt,
unsigned int level,
unsigned int slice);
bool
intel_miptree_sample_with_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_sample_with_hiz(struct brw_context *brw,
struct brw_mipmap_tree *mt);
bool
intel_miptree_set_clear_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
brw_miptree_set_clear_color(struct brw_context *brw,
struct brw_mipmap_tree *mt,
union isl_color_value clear_color);
/* Get a clear color suitable for filling out an ISL surface state. */
union isl_color_value
intel_miptree_get_clear_color(const struct intel_mipmap_tree *mt,
brw_miptree_get_clear_color(const struct brw_mipmap_tree *mt,
struct brw_bo **clear_color_bo,
uint64_t *clear_color_offset);
static inline int
intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
brw_miptree_blt_pitch(struct brw_mipmap_tree *mt)
{
int pitch = mt->surf.row_pitch_B;
if (mt->surf.tiling != ISL_TILING_LINEAR)
@ -709,12 +709,12 @@ intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
}
isl_memcpy_type
intel_miptree_get_memcpy_type(mesa_format tiledFormat, GLenum format, GLenum type,
brw_miptree_get_memcpy_type(mesa_format tiledFormat, GLenum format, GLenum type,
uint32_t *cpp);
static inline bool
intel_miptree_needs_fake_etc(struct brw_context *brw,
struct intel_mipmap_tree *mt)
brw_miptree_needs_fake_etc(struct brw_context *brw,
struct brw_mipmap_tree *mt)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
bool is_etc = _mesa_is_format_etc2(mt->format) ||
@ -724,15 +724,15 @@ intel_miptree_needs_fake_etc(struct brw_context *brw,
}
static inline bool
intel_miptree_has_etc_shadow(struct brw_context *brw,
struct intel_mipmap_tree *mt)
brw_miptree_has_etc_shadow(struct brw_context *brw,
struct brw_mipmap_tree *mt)
{
return intel_miptree_needs_fake_etc(brw, mt) && mt->shadow_mt;
return brw_miptree_needs_fake_etc(brw, mt) && mt->shadow_mt;
}
void
intel_miptree_update_etc_shadow_levels(struct brw_context *brw,
struct intel_mipmap_tree *mt);
brw_miptree_update_etc_shadow_levels(struct brw_context *brw,
struct brw_mipmap_tree *mt);
#ifdef __cplusplus
}

2
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
View File

@ -256,7 +256,7 @@ do_blit_bitmap( struct gl_context *ctx,
/* The blitter has no idea about fast color clears, so we need to resolve
* the miptree before we do anything.
*/
intel_miptree_access_raw(brw, irb->mt, irb->mt_level, irb->mt_layer, true);
brw_miptree_access_raw(brw, irb->mt, irb->mt_level, irb->mt_layer, true);
/* Chop it all into chunks that can be digested by hardware: */
for (py = 0; py < height; py += DY) {

2
src/mesa/drivers/dri/i965/intel_pixel_copy.c
View File

@ -168,7 +168,7 @@ do_blit_copypixels(struct gl_context * ctx,
dstx += srcx - orig_srcx;
dsty += srcy - orig_srcy;
if (!intel_miptree_blit(brw,
if (!brw_miptree_blit(brw,
read_irb->mt, read_irb->mt_level, read_irb->mt_layer,
srcx, srcy, read_fb->FlipY,
draw_irb->mt, draw_irb->mt_level, draw_irb->mt_layer,

12
src/mesa/drivers/dri/i965/intel_pixel_draw.c
View File

@ -83,7 +83,7 @@ do_blit_drawpixels(struct gl_context * ctx,
src_format = _mesa_get_srgb_format_linear(src_format);
dst_format = _mesa_get_srgb_format_linear(dst_format);
if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
if (!brw_miptree_blit_compatible_formats(src_format, dst_format)) {
DBG("%s: bad format for blit\n", __func__);
return false;
}
@ -111,8 +111,8 @@ do_blit_drawpixels(struct gl_context * ctx,
src_buffer = intel_bufferobj_buffer(brw, src, src_offset,
height * src_stride, false);
struct intel_mipmap_tree *pbo_mt =
intel_miptree_create_for_bo(brw,
struct brw_mipmap_tree *pbo_mt =
brw_miptree_create_for_bo(brw,
src_buffer,
irb->mt->format,
src_offset,
@ -123,18 +123,18 @@ do_blit_drawpixels(struct gl_context * ctx,
if (!pbo_mt)
return false;
if (!intel_miptree_blit(brw,
if (!brw_miptree_blit(brw,
pbo_mt, 0, 0,
0, 0, src_flip,
irb->mt, irb->mt_level, irb->mt_layer,
x, y, ctx->DrawBuffer->FlipY,
width, height, COLOR_LOGICOP_COPY)) {
DBG("%s: blit failed\n", __func__);
intel_miptree_release(&pbo_mt);
brw_miptree_release(&pbo_mt);
return false;
}
intel_miptree_release(&pbo_mt);
brw_miptree_release(&pbo_mt);
if (ctx->Query.CurrentOcclusionObject)
ctx->Query.CurrentOcclusionObject->Result += width * height;

6
src/mesa/drivers/dri/i965/intel_pixel_read.c
View File

@ -124,7 +124,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
if (rb->_BaseFormat == GL_RGB)
return false;
copy_type = intel_miptree_get_memcpy_type(rb->Format, format, type, &cpp);
copy_type = brw_miptree_get_memcpy_type(rb->Format, format, type, &cpp);
if (copy_type == ISL_MEMCPY_INVALID)
return false;
@ -149,7 +149,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
/* Since we are going to read raw data to the miptree, we need to resolve
* any pending fast color clears before we start.
*/
intel_miptree_access_raw(brw, irb->mt, irb->mt_level, irb->mt_layer, false);
brw_miptree_access_raw(brw, irb->mt, irb->mt_level, irb->mt_layer, false);
bo = irb->mt->bo;
@ -165,7 +165,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
}
unsigned slice_offset_x, slice_offset_y;
intel_miptree_get_image_offset(irb->mt, irb->mt_level, irb->mt_layer,
brw_miptree_get_image_offset(irb->mt, irb->mt_level, irb->mt_layer,
&slice_offset_x, &slice_offset_y);
xoffset += slice_offset_x;
yoffset += slice_offset_y;

10
src/mesa/drivers/dri/i965/intel_screen.c
View File

@ -488,12 +488,12 @@ intel_allocate_image(struct brw_screen *screen, int dri_format,
*/
static void
intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
struct intel_mipmap_tree *mt, GLuint level,
struct brw_mipmap_tree *mt, GLuint level,
GLuint zoffset)
{
intel_miptree_make_shareable(brw, mt);
brw_miptree_make_shareable(brw, mt);
intel_miptree_check_level_layer(mt, level, zoffset);
brw_miptree_check_level_layer(mt, level, zoffset);
image->width = minify(mt->surf.phys_level0_sa.width,
level - mt->first_level);
@ -501,7 +501,7 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
level - mt->first_level);
image->pitch = mt->surf.row_pitch_B;
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
image->offset = brw_miptree_get_tile_offsets(mt, level, zoffset,
&image->tile_x,
&image->tile_y);
@ -559,7 +559,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
}
irb = brw_renderbuffer(rb);
intel_miptree_make_shareable(brw, irb->mt);
brw_miptree_make_shareable(brw, irb->mt);
image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;

34
src/mesa/drivers/dri/i965/intel_tex.c
View File

@ -55,7 +55,7 @@ intelDeleteTextureObject(struct gl_context *ctx,
{
struct brw_texture_object *intelObj = brw_texture_object(texObj);
intel_miptree_release(&intelObj->mt);
brw_miptree_release(&intelObj->mt);
_mesa_delete_texture_object(ctx, texObj);
}
@ -87,13 +87,13 @@ intel_alloc_texture_image_buffer(struct gl_context *ctx,
return false;
if (intel_texobj->mt &&
intel_miptree_match_image(intel_texobj->mt, image)) {
intel_miptree_reference(&intel_image->mt, intel_texobj->mt);
brw_miptree_match_image(intel_texobj->mt, image)) {
brw_miptree_reference(&intel_image->mt, intel_texobj->mt);
DBG("%s: alloc obj %p level %d %dx%dx%d using object's miptree %p\n",
__func__, texobj, image->Level,
image->Width, image->Height, image->Depth, intel_texobj->mt);
} else {
intel_image->mt = intel_miptree_create_for_teximage(brw, intel_texobj,
intel_image->mt = brw_miptree_create_for_teximage(brw, intel_texobj,
intel_image,
MIPTREE_CREATE_DEFAULT);
if (!intel_image->mt)
@ -104,7 +104,7 @@ intel_alloc_texture_image_buffer(struct gl_context *ctx,
* whole object since our level didn't fit what was there
* before, and any lower levels would fit into our miptree.
*/
intel_miptree_reference(&intel_texobj->mt, intel_image->mt);
brw_miptree_reference(&intel_texobj->mt, intel_image->mt);
DBG("%s: alloc obj %p level %d %dx%dx%d using new miptree %p\n",
__func__, texobj, image->Level,
@ -141,12 +141,12 @@ intel_alloc_texture_storage(struct gl_context *ctx,
* one.
*/
if (!intel_texobj->mt ||
!intel_miptree_match_image(intel_texobj->mt, first_image) ||
!brw_miptree_match_image(intel_texobj->mt, first_image) ||
intel_texobj->mt->last_level != levels - 1) {
intel_miptree_release(&intel_texobj->mt);
brw_miptree_release(&intel_texobj->mt);
intel_get_image_dims(first_image, &width, &height, &depth);
intel_texobj->mt = intel_miptree_create(brw, texobj->Target,
intel_texobj->mt = brw_miptree_create(brw, texobj->Target,
first_image->TexFormat,
0, levels - 1,
width, height, depth,
@ -169,7 +169,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
if (!_swrast_init_texture_image(image))
return false;
intel_miptree_reference(&intel_image->mt, intel_texobj->mt);
brw_miptree_reference(&intel_image->mt, intel_texobj->mt);
}
}
@ -191,7 +191,7 @@ intel_free_texture_image_buffer(struct gl_context * ctx,
DBG("%s\n", __func__);
intel_miptree_release(&intelImage->mt);
brw_miptree_release(&intelImage->mt);
_swrast_free_texture_image_buffer(ctx, texImage);
}
@ -214,7 +214,7 @@ intel_map_texture_image(struct gl_context *ctx,
{
struct brw_context *brw = brw_context(ctx);
struct brw_texture_image *intel_image = brw_texture_image(tex_image);
struct intel_mipmap_tree *mt = intel_image->mt;
struct brw_mipmap_tree *mt = intel_image->mt;
ptrdiff_t stride;
/* Our texture data is always stored in a miptree. */
@ -224,13 +224,13 @@ intel_map_texture_image(struct gl_context *ctx,
assert(tex_image->TexObject->Target != GL_TEXTURE_1D_ARRAY ||
h == 1);
/* intel_miptree_map operates on a unified "slice" number that references the
/* brw_miptree_map operates on a unified "slice" number that references the
* cube face, since it's all just slices to the miptree code.
*/
if (tex_image->TexObject->Target == GL_TEXTURE_CUBE_MAP)
slice = tex_image->Face;
intel_miptree_map(brw, mt,
brw_miptree_map(brw, mt,
tex_image->Level + tex_image->TexObject->Attrib.MinLevel,
slice + tex_image->TexObject->Attrib.MinLayer,
x, y, w, h, mode,
@ -245,12 +245,12 @@ intel_unmap_texture_image(struct gl_context *ctx,
{
struct brw_context *brw = brw_context(ctx);
struct brw_texture_image *intel_image = brw_texture_image(tex_image);
struct intel_mipmap_tree *mt = intel_image->mt;
struct brw_mipmap_tree *mt = intel_image->mt;
if (tex_image->TexObject->Target == GL_TEXTURE_CUBE_MAP)
slice = tex_image->Face;
intel_miptree_unmap(brw, mt,
brw_miptree_unmap(brw, mt,
tex_image->Level + tex_image->TexObject->Attrib.MinLevel,
slice + tex_image->TexObject->Attrib.MinLayer);
}
@ -265,7 +265,7 @@ brw_texture_view(struct gl_context *ctx,
struct brw_texture_object *intel_orig_tex = brw_texture_object(origTexObj);
assert(intel_orig_tex->mt);
intel_miptree_reference(&intel_tex->mt, intel_orig_tex->mt);
brw_miptree_reference(&intel_tex->mt, intel_orig_tex->mt);
/* Since we can only make views of immutable-format textures,
* we can assume that everything is in origTexObj's miptree.
@ -284,7 +284,7 @@ brw_texture_view(struct gl_context *ctx,
struct gl_texture_image *image = texObj->Image[face][level];
struct brw_texture_image *intel_image = brw_texture_image(image);
intel_miptree_reference(&intel_image->mt, intel_orig_tex->mt);
brw_miptree_reference(&intel_image->mt, intel_orig_tex->mt);
}
}

10
src/mesa/drivers/dri/i965/intel_tex.h
View File

@ -46,11 +46,11 @@ void intelSetTexBuffer2(__DRIcontext *pDRICtx,
void intelReleaseTexBuffer(__DRIcontext *pDRICtx, GLint target,
__DRIdrawable *dPriv);
struct intel_mipmap_tree *
intel_miptree_create_for_teximage(struct brw_context *brw,
struct brw_texture_object *intelObj,
struct brw_texture_image *intelImage,
enum intel_miptree_create_flags flags);
struct brw_mipmap_tree *
brw_miptree_create_for_teximage(struct brw_context *brw,
struct brw_texture_object *intelObj,
struct brw_texture_image *intelImage,
enum brw_miptree_create_flags flags);
void intel_finalize_mipmap_tree(struct brw_context *brw,
struct gl_texture_object *tex_obj);

70
src/mesa/drivers/dri/i965/intel_tex_image.c
View File

@ -48,16 +48,16 @@ get_base_dim(unsigned old_base_dim, unsigned new_level_dim, unsigned level)
/* Work back from the specified level of the image to the baselevel and create a
* miptree of that size.
*/
struct intel_mipmap_tree *
intel_miptree_create_for_teximage(struct brw_context *brw,
struct brw_texture_object *intelObj,
struct brw_texture_image *intelImage,
enum intel_miptree_create_flags flags)
struct brw_mipmap_tree *
brw_miptree_create_for_teximage(struct brw_context *brw,
struct brw_texture_object *intelObj,
struct brw_texture_image *intelImage,
enum brw_miptree_create_flags flags)
{
GLuint lastLevel;
int width, height, depth;
unsigned old_width = 0, old_height = 0, old_depth = 0;
const struct intel_mipmap_tree *old_mt = intelObj->mt;
const struct brw_mipmap_tree *old_mt = intelObj->mt;
const unsigned level = intelImage->base.Base.Level;
intel_get_image_dims(&intelImage->base.Base, &width, &height, &depth);
@ -115,16 +115,16 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
width, height, depth) - 1;
}
return intel_miptree_create(brw,
intelObj->base.Target,
intelImage->base.Base.TexFormat,
0,
lastLevel,
width,
height,
depth,
MAX2(intelImage->base.Base.NumSamples, 1),
flags);
return brw_miptree_create(brw,
intelObj->base.Target,
intelImage->base.Base.TexFormat,
0,
lastLevel,
width,
height,
depth,
MAX2(intelImage->base.Base.NumSamples, 1),
flags);
}
static bool
@ -222,7 +222,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
if (ctx->_ImageTransferState)
return false;
copy_type = intel_miptree_get_memcpy_type(texImage->TexFormat, format, type,
copy_type = brw_miptree_get_memcpy_type(texImage->TexFormat, format, type,
&cpp);
if (copy_type == ISL_MEMCPY_INVALID)
return false;
@ -257,7 +257,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
assert(image->mt->surf.logical_level0_px.depth == 1);
assert(image->mt->surf.logical_level0_px.array_len == 1);
intel_miptree_access_raw(brw, image->mt, level, 0, true);
brw_miptree_access_raw(brw, image->mt, level, 0, true);
bo = image->mt->bo;
@ -287,7 +287,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
/* Adjust x and y offset based on miplevel */
unsigned level_x, level_y;
intel_miptree_get_image_offset(image->mt, level, 0, &level_x, &level_y);
brw_miptree_get_image_offset(image->mt, level, 0, &level_x, &level_y);
xoffset += level_x;
yoffset += level_y;
@ -318,7 +318,7 @@ intel_upload_tex(struct gl_context * ctx,
const struct gl_pixelstore_attrib *packing)
{
struct brw_context *brw = brw_context(ctx);
struct intel_mipmap_tree *mt = brw_texture_image(texImage)->mt;
struct brw_mipmap_tree *mt = brw_texture_image(texImage)->mt;
bool ok;
/* Check that there is actually data to store. */
@ -405,7 +405,7 @@ intel_set_texture_image_mt(struct brw_context *brw,
struct gl_texture_image *image,
GLenum internal_format,
mesa_format format,
struct intel_mipmap_tree *mt)
struct brw_mipmap_tree *mt)
{
struct gl_texture_object *texobj = image->TexObject;
@ -423,10 +423,10 @@ intel_set_texture_image_mt(struct brw_context *brw,
intel_image->base.RowStride = mt->surf.row_pitch_B / mt->cpp;
assert(mt->surf.row_pitch_B % mt->cpp == 0);
intel_miptree_reference(&intel_image->mt, mt);
brw_miptree_reference(&intel_image->mt, mt);
/* Immediately validate the image to the object. */
intel_miptree_reference(&intel_texobj->mt, mt);
brw_miptree_reference(&intel_texobj->mt, mt);
}
@ -488,7 +488,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
internal_format = GL_RGB;
}
intel_miptree_finish_external(brw, rb->mt);
brw_miptree_finish_external(brw, rb->mt);
_mesa_lock_texture(&brw->ctx, texObj);
texImage = _mesa_get_tex_image(ctx, texObj, target, 0);
@ -518,7 +518,7 @@ intelReleaseTexBuffer(__DRIcontext *pDRICtx, GLint target,
return;
}
/* The intel_miptree_prepare_external below as well as the finish_external
/* The brw_miptree_prepare_external below as well as the finish_external
* above in intelSetTexBuffer2 *should* do nothing. The BindTexImage call
* from both GLX and EGL has TexImage2D and not TexSubImage2D semantics so
* the texture is not immutable. This means that the user cannot create a
@ -545,7 +545,7 @@ intelReleaseTexBuffer(__DRIcontext *pDRICtx, GLint target,
* ever triggers this, we should at least warn them.
*/
if (intel_tex->mt->aux_buf &&
intel_miptree_get_aux_state(intel_tex->mt, 0, 0) !=
brw_miptree_get_aux_state(intel_tex->mt, 0, 0) !=
isl_drm_modifier_get_default_aux_state(intel_tex->mt->drm_modifier)) {
_mesa_warning(ctx, "Aux state changed between BindTexImage and "
"ReleaseTexImage. Most likely someone tried to draw "
@ -553,7 +553,7 @@ intelReleaseTexBuffer(__DRIcontext *pDRICtx, GLint target,
"image_load_store.");
}
intel_miptree_prepare_external(brw, intel_tex->mt);
brw_miptree_prepare_external(brw, intel_tex->mt);
_mesa_unlock_texture(&brw->ctx, tex_obj);
}
@ -582,10 +582,10 @@ intel_bind_renderbuffer_tex_image(struct gl_context *ctx,
0, rb->InternalFormat, rb->Format);
image->NumSamples = rb->NumSamples;
intel_miptree_reference(&intel_image->mt, irb->mt);
brw_miptree_reference(&intel_image->mt, irb->mt);
/* Immediately validate the image to the object. */
intel_miptree_reference(&intel_texobj->mt, intel_image->mt);
brw_miptree_reference(&intel_texobj->mt, intel_image->mt);
intel_texobj->needs_validate = true;
_mesa_unlock_texture(ctx, texobj);
@ -610,7 +610,7 @@ intel_image_target_texture(struct gl_context *ctx, GLenum target,
bool storage)
{
struct brw_context *brw = brw_context(ctx);
struct intel_mipmap_tree *mt;
struct brw_mipmap_tree *mt;
__DRIscreen *dri_screen = brw->screen->driScrnPriv;
__DRIimage *image;
@ -627,7 +627,7 @@ intel_image_target_texture(struct gl_context *ctx, GLenum target,
return;
}
mt = intel_miptree_create_for_dri_image(brw, image, target, image->format,
mt = brw_miptree_create_for_dri_image(brw, image, target, image->format,
false);
if (mt == NULL)
return;
@ -663,7 +663,7 @@ intel_image_target_texture(struct gl_context *ctx, GLenum target,
}
intel_set_texture_image_mt(brw, texImage, internal_format, mt->format, mt);
intel_miptree_release(&mt);
brw_miptree_release(&mt);
}
static void
@ -775,7 +775,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
if (texImage->_BaseFormat == GL_RGB)
return false;
copy_type = intel_miptree_get_memcpy_type(texImage->TexFormat, format, type,
copy_type = brw_miptree_get_memcpy_type(texImage->TexFormat, format, type,
&cpp);
if (copy_type == ISL_MEMCPY_INVALID)
return false;
@ -810,7 +810,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
assert(image->mt->surf.logical_level0_px.depth == 1);
assert(image->mt->surf.logical_level0_px.array_len == 1);
intel_miptree_access_raw(brw, image->mt, level, 0, true);
brw_miptree_access_raw(brw, image->mt, level, 0, true);
bo = image->mt->bo;
@ -837,7 +837,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
/* Adjust x and y offset based on miplevel */
unsigned level_x, level_y;
intel_miptree_get_image_offset(image->mt, level, 0, &level_x, &level_y);
brw_miptree_get_image_offset(image->mt, level, 0, &level_x, &level_y);
xoffset += level_x;
yoffset += level_y;

4
src/mesa/drivers/dri/i965/intel_tex_obj.h
View File

@ -48,7 +48,7 @@ struct brw_texture_object
/* The miptree of pixel data for the texture (if !needs_validate). After
* validation, the images will also have references to the same mt.
*/
struct intel_mipmap_tree *mt;
struct brw_mipmap_tree *mt;
/**
* Set when mipmap trees in the texture images of this texture object
@ -79,7 +79,7 @@ struct brw_texture_image
* Else if intelImage->base.Buffer != NULL, image is stored there.
* Else there is no image data.
*/
struct intel_mipmap_tree *mt;
struct brw_mipmap_tree *mt;
};
static inline struct brw_texture_object *

28
src/mesa/drivers/dri/i965/intel_tex_validate.c
View File

@ -109,10 +109,10 @@ intel_finalize_mipmap_tree(struct brw_context *brw,
* target, imageFormat, etc.
*/
if (intelObj->mt &&
(!intel_miptree_match_image(intelObj->mt, &firstImage->base.Base) ||
(!brw_miptree_match_image(intelObj->mt, &firstImage->base.Base) ||
validate_first_level < intelObj->mt->first_level ||
validate_last_level > intelObj->mt->last_level)) {
intel_miptree_release(&intelObj->mt);
brw_miptree_release(&intelObj->mt);
}
@ -150,16 +150,16 @@ intel_finalize_mipmap_tree(struct brw_context *brw,
_mesa_get_format_name(firstImage->base.Base.TexFormat),
width, height, depth, validate_last_level + 1);
intelObj->mt = intel_miptree_create(brw,
intelObj->base.Target,
firstImage->base.Base.TexFormat,
0, /* first_level */
validate_last_level,
width,
height,
depth,
1 /* num_samples */,
MIPTREE_CREATE_BUSY);
intelObj->mt = brw_miptree_create(brw,
intelObj->base.Target,
firstImage->base.Base.TexFormat,
0, /* first_level */
validate_last_level,
width,
height,
depth,
1 /* num_samples */,
MIPTREE_CREATE_BUSY);
if (!intelObj->mt)
return;
}
@ -176,13 +176,13 @@ intel_finalize_mipmap_tree(struct brw_context *brw,
break;
if (intelObj->mt != intelImage->mt)
intel_miptree_copy_teximage(brw, intelImage, intelObj->mt);
brw_miptree_copy_teximage(brw, intelImage, intelObj->mt);
/* After we're done, we'd better agree that our layout is
* appropriate, or we'll end up hitting this function again on the
* next draw
*/
assert(intel_miptree_match_image(intelObj->mt, &intelImage->base.Base));
assert(brw_miptree_match_image(intelObj->mt, &intelImage->base.Base));
}
}