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intel/isl: Resize clear color buffer to full cacheline 

Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.

v2 (Nanley): In the title s/Align/Resize/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
This commit is contained in:
Rafael Antognolli 2019-04-16 16:31:06 +03:00 committed by Topi Pohjolainen
parent 45957c05b0
commit f2041d2a92
1 changed files with 2 additions and 1 deletions
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src/intel/isl/isl.c
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@ -122,7 +122,8 @@ isl_device_init(struct isl_device *dev,
dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
dev->ss.align = isl_align(dev->ss.size, 32);
dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
dev->ss.clear_color_state_size =
isl_align(CLEAR_COLOR_length(info) * 4, 64);
dev->ss.clear_color_state_offset =
RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;