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radv: Fix various non-critical integer overflows 

The result of 0xf << 28 is a signed integer and hence overflows into the sign
bit. In practice compilers did the right thing here, since the intent of the
code was unsigned arithmetic anyway.

These conditions were observed in:
* dEQP-VK.pipeline.image.suballocation.sampling_type.combined.view_type.1d.format.r4g4b4a4_unorm_pack16.count_8.size.512x1
* dEQP-VK.binding_model.descriptorset_random.sets32.noarray.ubolimitlow.sbolimitlow.sampledimglow.outimgonly.noiub.nouab.frag.ialimithigh.0

Cc: mesa-stable
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6568>
This commit is contained in:
Tony Wasserka 2020-09-02 18:13:57 +02:00 committed by Marge Bot
parent a99ae1943d
commit f18fc34c4d
3 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/amd/vulkan/radv_pipeline.c
View File

@ -543,7 +543,7 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
*/
num_targets = (util_last_bit(col_format) + 3) / 4;
for (unsigned i = 0; i < num_targets; i++) {
if (!(col_format & (0xf << (i * 4)))) {
if (!(col_format & (0xfu << (i * 4)))) {
col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
}
}
@ -681,7 +681,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
continue;
blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
blend.cb_target_enabled_4bit |= 0xf << (4 * i);
blend.cb_target_enabled_4bit |= 0xfu << (4 * i);
if (!att->blendEnable) {
blend.cb_blend_control[i] = blend_cntl;
continue;
@ -701,9 +701,9 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
}
radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
0x7 << (4 * i));
0x7u << (4 * i));
radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
0x8 << (4 * i));
0x8u << (4 * i));
/* Blending optimizations for RB+.
* These transformations don't change the behavior.

2
src/amd/vulkan/radv_shader_args.c
View File

@ -68,7 +68,7 @@ set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx)
set_loc(ud_info, sgpr_idx, 1);
locs->descriptor_sets_enabled |= 1 << idx;
locs->descriptor_sets_enabled |= 1u << idx;
}
struct user_sgpr_info {

8
src/amd/vulkan/radv_shader_info.c
View File

@ -29,7 +29,7 @@
static void mark_sampler_desc(const nir_variable *var,
struct radv_shader_info *info)
{
info->desc_set_used_mask |= (1 << var->data.descriptor_set);
info->desc_set_used_mask |= (1u << var->data.descriptor_set);
}
static void mark_ls_output(struct radv_shader_info *info,
@ -288,7 +288,7 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
gather_push_constant_info(nir, instr, info);
break;
case nir_intrinsic_vulkan_resource_index:
info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
info->desc_set_used_mask |= (1u << nir_intrinsic_desc_set(instr));
break;
case nir_intrinsic_image_deref_load:
case nir_intrinsic_image_deref_store:
@ -853,8 +853,8 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
*/
unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4;
for (unsigned i = 0; i < num_targets; i++) {
if (!(info->ps.cb_shader_mask & (0xf << (i * 4)))) {
info->ps.cb_shader_mask |= 0xf << (i * 4);
if (!(info->ps.cb_shader_mask & (0xfu << (i * 4)))) {
info->ps.cb_shader_mask |= 0xfu << (i * 4);
}
}