r300g: add is_rv350 flag
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35489ef285
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@ -371,4 +371,6 @@ void r300_parse_chipset(struct r300_capabilities* caps)
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fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n",
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fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n",
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caps->pci_id);
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caps->pci_id);
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}
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}
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caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;
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}
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}
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@ -42,18 +42,28 @@ struct r300_capabilities {
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unsigned num_tex_units;
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unsigned num_tex_units;
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/* Whether or not TCL is physically present */
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/* Whether or not TCL is physically present */
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boolean has_tcl;
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boolean has_tcl;
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/* Whether or not this is R400. The differences compared to their R3xx
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/* Whether or not this is RV350 or newer, including all r400 and r500
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* chipsets. The differences compared to the oldest r300 chips are:
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* - Blend LTE/GTE thresholds
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* - Better MACRO_SWITCH in texture tiling
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* - Half float vertex
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* - More HyperZ optimizations */
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boolean is_rv350;
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/* Whether or not this is R400. The differences compared their rv350
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* cousins are:
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* cousins are:
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* - Extended fragment shader registers
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* - Extended fragment shader registers
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* - Blend LTE/GTE thresholds */
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* - 3DC texture compression (RGTC2) */
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boolean is_r400;
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boolean is_r400;
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/* Whether or not this is an RV515 or newer; R500s have many differences
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/* Whether or not this is an RV515 or newer; R500s have many differences
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* that require extra consideration, compared to their R3xx cousins:
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* that require extra consideration, compared to their rv350 cousins:
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* - Extra bit of width and height on texture sizes
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* - Extra bit of width and height on texture sizes
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* - Blend color is split across two registers
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* - Blend color is split across two registers
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* - Blend LTE/GTE thresholds
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* - Universal Shader (US) block used for fragment shaders
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* - Universal Shader (US) block used for fragment shaders
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* - FP16 blending and multisampling */
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* - FP16 blending and multisampling
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* - Full RGTC texture compression
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* - 24-bit depth textures
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* - Stencil back-face reference value
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* - Ability to render up to 2^24 - 1 vertices with signed index offset */
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boolean is_r500;
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boolean is_r500;
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/* Whether or not the second pixel pipe is accessed with the high bit */
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/* Whether or not the second pixel pipe is accessed with the high bit */
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boolean high_second_pipe;
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boolean high_second_pipe;
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@ -41,10 +41,9 @@ struct pipe_viewport_state r300_viewport_identity = {
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void r300_emit_invariant_state(struct r300_context* r300,
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void r300_emit_invariant_state(struct r300_context* r300,
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unsigned size, void* state)
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unsigned size, void* state)
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{
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{
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struct r300_capabilities* caps = &r300_screen(r300->context.screen)->caps;
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CS_LOCALS(r300);
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CS_LOCALS(r300);
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BEGIN_CS(12 + (caps->has_tcl ? 2: 0));
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BEGIN_CS(12 + (r300->screen->caps.has_tcl ? 2 : 0));
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/*** Graphics Backend (GB) ***/
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/*** Graphics Backend (GB) ***/
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/* Subpixel multisampling for AA
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/* Subpixel multisampling for AA
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@ -66,7 +65,7 @@ void r300_emit_invariant_state(struct r300_context* r300,
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/* Sign/normalize control */
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/* Sign/normalize control */
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OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
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OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
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/* TCL-only stuff */
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/* TCL-only stuff */
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if (caps->has_tcl) {
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if (r300->screen->caps.has_tcl) {
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/* Amount of time to wait for vertex fetches in PVS */
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/* Amount of time to wait for vertex fetches in PVS */
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OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
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OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
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}
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}
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@ -74,10 +73,10 @@ void r300_emit_invariant_state(struct r300_context* r300,
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END_CS;
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END_CS;
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/* XXX unsorted stuff from surface_fill */
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/* XXX unsorted stuff from surface_fill */
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BEGIN_CS(38 + (caps->has_tcl ? 7 : 0) +
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BEGIN_CS(38 + (r300->screen->caps.has_tcl ? 7 : 0) +
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(caps->family >= CHIP_FAMILY_RV350 ? 4 : 0));
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(r300->screen->caps.is_rv350 ? 4 : 0));
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if (caps->has_tcl) {
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if (r300->screen->caps.has_tcl) {
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/*Flushing PVS is required before the VAP_GB registers can be changed*/
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/*Flushing PVS is required before the VAP_GB registers can be changed*/
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
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OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
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OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
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@ -107,7 +106,7 @@ void r300_emit_invariant_state(struct r300_context* r300,
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OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
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OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
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OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
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OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
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if (caps->family >= CHIP_FAMILY_RV350) {
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if (r300->screen->caps.is_rv350) {
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
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}
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}
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@ -787,7 +787,7 @@ static void r300_setup_miptree(struct r300_screen* screen,
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{
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{
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struct pipe_resource* base = &tex->b.b;
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struct pipe_resource* base = &tex->b.b;
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unsigned stride, size, layer_size, nblocksy, i;
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unsigned stride, size, layer_size, nblocksy, i;
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boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_RV350;
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boolean rv350_mode = screen->caps.is_rv350;
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SCREEN_DBG(screen, DBG_TEX, "r300: Making miptree for texture, format %s\n",
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SCREEN_DBG(screen, DBG_TEX, "r300: Making miptree for texture, format %s\n",
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util_format_name(base->format));
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util_format_name(base->format));
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@ -834,7 +834,7 @@ static void r300_setup_tiling(struct pipe_screen *screen,
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{
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{
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struct r300_winsys_screen *rws = (struct r300_winsys_screen *)screen->winsys;
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struct r300_winsys_screen *rws = (struct r300_winsys_screen *)screen->winsys;
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enum pipe_format format = tex->b.b.format;
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enum pipe_format format = tex->b.b.format;
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boolean rv350_mode = r300_screen(screen)->caps.family >= CHIP_FAMILY_RV350;
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boolean rv350_mode = r300_screen(screen)->caps.is_rv350;
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boolean is_zb = util_format_is_depth_or_stencil(format);
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boolean is_zb = util_format_is_depth_or_stencil(format);
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boolean dbg_no_tiling = SCREEN_DBG_ON(r300_screen(screen), DBG_NO_TILING);
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boolean dbg_no_tiling = SCREEN_DBG_ON(r300_screen(screen), DBG_NO_TILING);
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